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Commit b51adc77 authored by Yue Hin Lau's avatar Yue Hin Lau Committed by Alex Deucher
Browse files

drm/amd/display: Only blank DCN when we have set_blank implementation 



Also rename timing_generator to optc

Signed-off-by: default avatarYue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: default avatarEric Bernstein <Eric.Bernstein@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 39f26499

drivers/gpu/drm/amd/display/dc/dcn10/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ 
# Makefile for DCN.



DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \

		dcn10_dpp.o dcn10_opp.o dcn10_timing_generator.o \

		dcn10_dpp.o dcn10_opp.o dcn10_optc.o \

		dcn10_hubp.o dcn10_mpc.o \

		dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_cm_common.o \

		dcn10_hubbub.o

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+26 −7
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ 
#include "dce/dce_hwseq.h"

#include "abm.h"

#include "dmcu.h"

#include "dcn10/dcn10_timing_generator.h"

#include "dcn10_optc.h"

#include "dcn10/dcn10_dpp.h"

#include "dcn10/dcn10_mpc.h"

#include "timing_generator.h"
@@ -465,6 +465,8 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( 
	bool enableStereo    = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ?

			false:true;

	bool rightEyePolarity = stream->timing.flags.RIGHT_EYE_3D_POLARITY;

	int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;

	int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;



	/* by upper caller loop, pipe0 is parent pipe and be called first.

	 * back end is set up by for pipe0. Other children pipe share back end
@@ -518,11 +520,14 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( 
	/* program otg blank color */

	color_space = stream->output_color_space;

	color_space_to_black_color(dc, color_space, &black_color);



	if (pipe_ctx->stream_res.tg->funcs->set_blank_color)

		pipe_ctx->stream_res.tg->funcs->set_blank_color(

				pipe_ctx->stream_res.tg,

				&black_color);



	if (!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {

	if (pipe_ctx->stream_res.tg->funcs->is_blanked &&

			!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {

		pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);

		hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);

		false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
@@ -1808,6 +1813,10 @@ static void program_all_pipe_in_tree( 
		struct pipe_ctx *pipe_ctx,

		struct dc_state *context)

{

	struct dc_stream_state *stream = pipe_ctx->stream;

	int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;

	int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;



	if (pipe_ctx->top_pipe == NULL) {



		pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
@@ -1818,7 +1827,11 @@ static void program_all_pipe_in_tree( 


		pipe_ctx->stream_res.tg->funcs->program_global_sync(

				pipe_ctx->stream_res.tg);

		pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, !is_pipe_tree_visible(pipe_ctx));



		if (pipe_ctx->stream_res.tg->funcs->set_blank)

			pipe_ctx->stream_res.tg->funcs->set_blank(

					pipe_ctx->stream_res.tg,

					!is_pipe_tree_visible(pipe_ctx));

	}



	if (pipe_ctx->plane_state != NULL) {
@@ -1925,9 +1938,12 @@ static void dcn10_apply_ctx_for_surface( 
{

	int i;

	struct timing_generator *tg;

	struct output_pixel_processor *opp;

	bool removed_pipe[4] = { false };

	unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;

	bool program_water_mark = false;

	int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;

	int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;



	struct pipe_ctx *top_pipe_to_program =

			find_top_pipe_for_stream(dc, context, stream);
@@ -1935,6 +1951,8 @@ static void dcn10_apply_ctx_for_surface( 
	if (!top_pipe_to_program)

		return;



	opp = top_pipe_to_program->stream_res.opp;



	tg = top_pipe_to_program->stream_res.tg;



	tg->funcs->lock(tg);
@@ -1942,6 +1960,7 @@ static void dcn10_apply_ctx_for_surface( 
	if (num_planes == 0) {



		/* OTG blank before remove all front end */

		if (tg->funcs->set_blank)

			tg->funcs->set_blank(tg, true);

	}

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c→drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c

+3 −3
Original line number Diff line number Diff line
@@ -23,8 +23,9 @@ 
 *

 */





#include "reg_helper.h"

#include "dcn10_timing_generator.h"

#include "dcn10_optc.h"

#include "dc.h"



#define REG(reg)\
@@ -251,8 +252,7 @@ void optc1_program_timing( 
		v_init = v_init / 2;

		if ((optc->dlg_otg_param.vstartup_start/2)*2 > asic_blank_end)

			v_fp2 = v_fp2 / 2;

	}

	else

	} else

		REG_UPDATE(OTG_INTERLACE_CONTROL,

				OTG_INTERLACE_ENABLE, 0);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ 
#include "dcn10/dcn10_mpc.h"

#include "irq/dcn10/irq_service_dcn10.h"

#include "dcn10/dcn10_dpp.h"

#include "dcn10/dcn10_timing_generator.h"

#include "dcn10_optc.h"

#include "dcn10/dcn10_hw_sequencer.h"

#include "dce110/dce110_hw_sequencer.h"

#include "dcn10/dcn10_opp.h"