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Commit b4ed372b authored by Stephen Hemminger's avatar Stephen Hemminger Committed by Jeff Garzik
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sky2: dont set bogus bit in PHY register 



This code inherited from the sk98lin driver is incorrect on the Yukon2.
The GPHY_CTRL register values are specific to the internal PHY of the chip
and the values used were leftovers.
Driver was setting bit 13 which is now the INT polarity for the PHY!

Signed-off-by: default avatarStephen Hemminger <shemminger@linux-foundation.org>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent 8903bab0

drivers/net/sky2.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -658,7 +658,7 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port) 
	const u8 *addr = hw->dev[port]->dev_addr;

	const u8 *addr = hw->dev[port]->dev_addr;





	sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

	sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

	sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);

	sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);





	sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);

	sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);

drivers/net/sky2.h

+0 −22
Original line number Original line Diff line number Diff line
@@ -1732,28 +1732,6 @@ enum { 




/*	GPHY_CTRL		32 bit	GPHY Control Reg (YUKON only) */

/*	GPHY_CTRL		32 bit	GPHY Control Reg (YUKON only) */

enum {

enum {

	GPC_SEL_BDT	= 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */

	GPC_INT_POL_HI	= 1<<27, /* IRQ Polarity is Active HIGH */

	GPC_75_OHM	= 1<<26, /* Use 75 Ohm Termination instead of 50 */

	GPC_DIS_FC	= 1<<25, /* Disable Automatic Fiber/Copper Detection */

	GPC_DIS_SLEEP	= 1<<24, /* Disable Energy Detect */

	GPC_HWCFG_M_3	= 1<<23, /* HWCFG_MODE[3] */

	GPC_HWCFG_M_2	= 1<<22, /* HWCFG_MODE[2] */

	GPC_HWCFG_M_1	= 1<<21, /* HWCFG_MODE[1] */

	GPC_HWCFG_M_0	= 1<<20, /* HWCFG_MODE[0] */

	GPC_ANEG_0	= 1<<19, /* ANEG[0] */

	GPC_ENA_XC	= 1<<18, /* Enable MDI crossover */

	GPC_DIS_125	= 1<<17, /* Disable 125 MHz clock */

	GPC_ANEG_3	= 1<<16, /* ANEG[3] */

	GPC_ANEG_2	= 1<<15, /* ANEG[2] */

	GPC_ANEG_1	= 1<<14, /* ANEG[1] */

	GPC_ENA_PAUSE	= 1<<13, /* Enable Pause (SYM_OR_REM) */

	GPC_PHYADDR_4	= 1<<12, /* Bit 4 of Phy Addr */

	GPC_PHYADDR_3	= 1<<11, /* Bit 3 of Phy Addr */

	GPC_PHYADDR_2	= 1<<10, /* Bit 2 of Phy Addr */

	GPC_PHYADDR_1	= 1<<9,	 /* Bit 1 of Phy Addr */

	GPC_PHYADDR_0	= 1<<8,	 /* Bit 0 of Phy Addr */

						/* Bits  7..2:	reserved */

	GPC_RST_CLR	= 1<<1,	/* Clear GPHY Reset */

	GPC_RST_CLR	= 1<<1,	/* Clear GPHY Reset */

	GPC_RST_SET	= 1<<0,	/* Set   GPHY Reset */

	GPC_RST_SET	= 1<<0,	/* Set   GPHY Reset */

};

};