Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b4d7f3e2 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "msm: npu: Limit maximum NPU frequency based on the efuse value"

parents ec90749b f964319f

drivers/media/platform/msm/npu/npu_dev.c

+4 −5
Original line number Diff line number Diff line
@@ -1802,13 +1802,12 @@ static int npu_of_parse_pwrlevels(struct npu_device *npu_dev, 
		NPU_DBG("fmax %x\n", fmax);



		switch (fmax) {

		case 1:

		case 2:

			fmax_pwrlvl = NPU_PWRLEVEL_NOM;

			break;

		case 3:

		case 0x34:

			fmax_pwrlvl = NPU_PWRLEVEL_SVS_L1;

			break;

		case 0x48:

			fmax_pwrlvl = NPU_PWRLEVEL_NOM;

			break;

		default:

			fmax_pwrlvl = pwr->max_pwrlevel;

			break;

drivers/media/platform/msm/npu/npu_hw_access.h

+3 −3
Original line number Diff line number Diff line
@@ -19,9 +19,9 @@ 
#define IPC_MEM_OFFSET_FROM_SSTCM 0x00018000

#define SYS_CACHE_SCID 23



#define QFPROM_FMAX_REG_OFFSET 0x000001C8

#define QFPROM_FMAX_BITS_MASK  0x0000000C

#define QFPROM_FMAX_BITS_SHIFT 2

#define QFPROM_FMAX_REG_OFFSET 0x00006010

#define QFPROM_FMAX_BITS_MASK  0x0003FC00

#define QFPROM_FMAX_BITS_SHIFT 10



#define REGW(npu_dev, off, val) npu_core_reg_write(npu_dev, off, val)

#define REGR(npu_dev, off) npu_core_reg_read(npu_dev, off)