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Commit b4ac5f31 authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: bengal: Update PLL voting to MX rail 



The current voting of the PLL is to CX, but in hardware the PLLs are
connected on the MX Rail. Also separate the VCO tables for PLL0 and
PLL1.

Change-Id: I8a196568b3f5a74f5da85d8240c4ab5206e65592
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 04301c31

drivers/clk/qcom/gpucc-bengal.c

+23 −11
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.

 */



#define pr_fmt(fmt) "clk: %s: " fmt, __func__
@@ -26,6 +26,7 @@ 
#define CX_GMU_CBCR_WAKE_SHIFT          8



static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);

static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner);



enum {

	P_BI_TCXO,
@@ -80,15 +81,18 @@ static const char * const gpu_cc_parent_names_1[] = { 


static struct pll_vco default_vco[] = {

	{ 1000000000, 2000000000, 0 },

	{ 750000000, 1500000000, 1 },

};



static struct pll_vco pll1_vco[] = {

	{ 500000000, 1000000000, 2 },

	{ 250000000, 500000000, 3 },

};



static const struct alpha_pll_config gpu_cc_pll0_config = {

	.l = 0x1B,

	.alpha = 0x55000000,

	.alpha_hi = 0xB5,

	.l = 0x3E,

	.alpha = 0x00000000,

	.alpha_hi = 0x80,

	.vco_val = 0x0 << 20,

	.vco_mask = GENMASK(21, 20),

	.alpha_en_mask = BIT(24),

	.main_output_mask = BIT(0),

	.aux_output_mask = BIT(1),
@@ -98,7 +102,7 @@ static const struct alpha_pll_config gpu_cc_pll0_config = { 
	.test_ctl_hi_mask = 0x1,

};



/* 532MHz configuration */

/* 1200MHz configuration */

static struct clk_alpha_pll gpu_cc_pll0 = {

	.offset = 0x0,

	.vco_table = default_vco,
@@ -111,7 +115,7 @@ static struct clk_alpha_pll gpu_cc_pll0 = { 
			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.ops = &clk_alpha_pll_ops,

			.vdd_class = &vdd_cx,

			.vdd_class = &vdd_mx,

			.num_rate_max = VDD_NUM,

			.rate_max = (unsigned long[VDD_NUM]) {

				[VDD_MIN] = 1000000000,
@@ -158,8 +162,8 @@ static const struct alpha_pll_config gpu_cc_pll1_config = { 


static struct clk_alpha_pll gpu_cc_pll1 = {

	.offset = 0x100,

	.vco_table = default_vco,

	.num_vco = ARRAY_SIZE(default_vco),

	.vco_table = pll1_vco,

	.num_vco = ARRAY_SIZE(pll1_vco),

	.flags = SUPPORTS_DYNAMIC_UPDATE,

	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],

	.clkr = {
@@ -168,7 +172,7 @@ static struct clk_alpha_pll gpu_cc_pll1 = { 
			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.ops = &clk_alpha_pll_ops,

			.vdd_class = &vdd_cx,

			.vdd_class = &vdd_mx,

			.num_rate_max = VDD_NUM,

			.rate_max = (unsigned long[VDD_NUM]) {

				[VDD_MIN] = 1000000000,
@@ -474,6 +478,14 @@ static int gpucc_bengal_probe(struct platform_device *pdev) 
		return PTR_ERR(vdd_cx.regulator[0]);

	}



	vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx");

	if (IS_ERR(vdd_mx.regulator[0])) {

		if (!(PTR_ERR(vdd_mx.regulator[0]) == -EPROBE_DEFER))

			dev_err(&pdev->dev,

				"Unable to get vdd_mx regulator\n");

		return PTR_ERR(vdd_mx.regulator[0]);

	}



	regmap = qcom_cc_map(pdev, &gpu_cc_bengal_desc);

	if (IS_ERR(regmap))

		return PTR_ERR(regmap);