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Commit b3e7f866 authored by Lionel Landwerlin's avatar Lionel Landwerlin
Browse files

drm/i915/debugfs: reuse max slice/subslices already stored in sseu 



Now that we have that information in topology fields, let's just reuse it.

v2: Style tweaks (Tvrtko)

Signed-off-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180306122857.27317-3-lionel.g.landwerlin@intel.com
parent 8cc76693

drivers/gpu/drm/i915/i915_debugfs.c

+11 −16
Original line number Diff line number Diff line
@@ -4338,11 +4338,11 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, 
				     struct sseu_dev_info *sseu)

{

	const struct intel_device_info *info = INTEL_INFO(dev_priv);

	int s_max = 6, ss_max = 4;

	int s, ss;

	u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];

	u32 s_reg[info->sseu.max_slices];

	u32 eu_reg[2 * info->sseu.max_subslices], eu_mask[2];



	for (s = 0; s < s_max; s++) {

	for (s = 0; s < info->sseu.max_slices; s++) {

		/*

		 * FIXME: Valid SS Mask respects the spec and read

		 * only valid bits for those registers, excluding reserverd
@@ -4364,7 +4364,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, 
		     GEN9_PGCTL_SSB_EU210_ACK |

		     GEN9_PGCTL_SSB_EU311_ACK;



	for (s = 0; s < s_max; s++) {

	for (s = 0; s < info->sseu.max_slices; s++) {

		if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)

			/* skip disabled slice */

			continue;
@@ -4372,7 +4372,7 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, 
		sseu->slice_mask |= BIT(s);

		sseu->subslice_mask[s] = info->sseu.subslice_mask[s];



		for (ss = 0; ss < ss_max; ss++) {

		for (ss = 0; ss < info->sseu.max_subslices; ss++) {

			unsigned int eu_cnt;



			if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
@@ -4392,17 +4392,12 @@ static void gen10_sseu_device_status(struct drm_i915_private *dev_priv, 
static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,

				    struct sseu_dev_info *sseu)

{

	int s_max = 3, ss_max = 4;

	const struct intel_device_info *info = INTEL_INFO(dev_priv);

	int s, ss;

	u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];



	/* BXT has a single slice and at most 3 subslices. */

	if (IS_GEN9_LP(dev_priv)) {

		s_max = 1;

		ss_max = 3;

	}

	u32 s_reg[info->sseu.max_slices];

	u32 eu_reg[2 * info->sseu.max_subslices], eu_mask[2];



	for (s = 0; s < s_max; s++) {

	for (s = 0; s < info->sseu.max_slices; s++) {

		s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));

		eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));

		eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
@@ -4417,7 +4412,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, 
		     GEN9_PGCTL_SSB_EU210_ACK |

		     GEN9_PGCTL_SSB_EU311_ACK;



	for (s = 0; s < s_max; s++) {

	for (s = 0; s < info->sseu.max_slices; s++) {

		if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)

			/* skip disabled slice */

			continue;
@@ -4428,7 +4423,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, 
			sseu->subslice_mask[s] =

				INTEL_INFO(dev_priv)->sseu.subslice_mask[s];



		for (ss = 0; ss < ss_max; ss++) {

		for (ss = 0; ss < info->sseu.max_subslices; ss++) {

			unsigned int eu_cnt;



			if (IS_GEN9_LP(dev_priv)) {

drivers/gpu/drm/i915/intel_device_info.c

+1 −1

File changed.

Contains only whitespace changes.