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Commit b3766c51 authored by Jose Alarcon's avatar Jose Alarcon Committed by Shawn Guo
Browse files

ARM: dts: imx6q-bx50v3: Enable i2c recovery mechanism 



This commit enables i2c recovery, supported by the i2c core subsystem.
It defines the required GPIOs for SDA and SCL lines.

Signed-off-by: default avatarJose Alarcon <jose.alarcon@ge.com>
Signed-off-by: default avatarNandor Han <nandor.han@ge.com>
Signed-off-by: default avatarRomain Perier <romain.perier@collabora.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent c6a9f138

arch/arm/boot/dts/imx6q-bx50v3.dtsi

+42 −0
Original line number Diff line number Diff line
@@ -111,6 +111,11 @@ 
};



&i2c1 {

	pinctrl-names = "default", "gpio";

	pinctrl-1 = <&pinctrl_i2c1_gpio>;

	sda-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>;

	scl-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;



	pca9547: mux@70 {

		compatible = "nxp,pca9547";

		reg = <0x70>;
@@ -261,6 +266,43 @@ 
	};

};



&i2c2 {

	pinctrl-names = "default", "gpio";

	pinctrl-1 = <&pinctrl_i2c2_gpio>;

	sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;

	scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;

};



&i2c3 {

	pinctrl-names = "default", "gpio";

	pinctrl-1 = <&pinctrl_i2c3_gpio>;

	sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;

	scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;

};



&iomuxc {

	pinctrl_i2c1_gpio: i2c1gpiogrp {

		fsl,pins = <

			MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26	0x1b0b0

			MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27	0x1b0b0

		>;

	};



	pinctrl_i2c2_gpio: i2c2gpiogrp {

		fsl,pins = <

			MX6QDL_PAD_KEY_COL3__GPIO4_IO12	0x1b0b0

			MX6QDL_PAD_KEY_ROW3__GPIO4_IO13	0x1b0b0

		>;

	};



	pinctrl_i2c3_gpio: i2c3gpiogrp {

		fsl,pins = <

			MX6QDL_PAD_GPIO_3__GPIO1_IO03	0x1b0b0

			MX6QDL_PAD_GPIO_6__GPIO1_IO06	0x1b0b0

		>;

	};

};



&usdhc4 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc4>;