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Commit b360ada3 authored by Michael Turquette's avatar Michael Turquette
Browse files

Merge tag 'tegra-for-4.5-clk' of... 

Merge tag 'tegra-for-4.5-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next

clk: tegra: Changes for v4.5-rc1

This set of changes adds support for the Tegra210 SoC and contains a
couple fixes and cleanups.
parents 7ed88aa2 2d7f61f3

Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt

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+56 −0
Original line number Diff line number Diff line 
NVIDIA Tegra210 Clock And Reset Controller



This binding uses the common clock binding:

Documentation/devicetree/bindings/clock/clock-bindings.txt



The CAR (Clock And Reset) Controller on Tegra is the HW module responsible

for muxing and gating Tegra's clocks, and setting their rates.



Required properties :

- compatible : Should be "nvidia,tegra210-car"

- reg : Should contain CAR registers location and length

- clocks : Should contain phandle and clock specifiers for two clocks:

  the 32 KHz "32k_in".

- #clock-cells : Should be 1.

  In clock consumers, this cell represents the clock ID exposed by the

  CAR. The assignments may be found in header file

  <dt-bindings/clock/tegra210-car.h>.

- #reset-cells : Should be 1.

  In clock consumers, this cell represents the bit number in the CAR's

  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.



Example SoC include file:



/ {

	tegra_car: clock {

		compatible = "nvidia,tegra210-car";

		reg = <0x60006000 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	usb@c5004000 {

		clocks = <&tegra_car TEGRA210_CLK_USB2>;

	};

};



Example board file:



/ {

	clocks {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <0>;



		clk_32k: clock@1 {

			compatible = "fixed-clock";

			reg = <1>;

			#clock-cells = <0>;

			clock-frequency = <32768>;

		};

	};



	&tegra_car {

		clocks = <&clk_32k>;

	};

};

drivers/clk/tegra/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -20,3 +20,4 @@ obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o 
obj-$(CONFIG_ARCH_TEGRA_124_SOC)	+= clk-tegra124-dfll-fcpu.o

obj-$(CONFIG_ARCH_TEGRA_132_SOC)	+= clk-tegra124.o

obj-y					+= cvb.o

obj-$(CONFIG_ARCH_TEGRA_210_SOC)	+= clk-tegra210.o

drivers/clk/tegra/clk-id.h

+74 −1
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ enum clk_id { 
	tegra_clk_amx1,

	tegra_clk_apbdma,

	tegra_clk_apbif,

	tegra_clk_ape,

	tegra_clk_audio0,

	tegra_clk_audio0_2x,

	tegra_clk_audio0_mux,
@@ -38,6 +39,7 @@ enum clk_id { 
	tegra_clk_cile,

	tegra_clk_clk_32k,

	tegra_clk_clk72Mhz,

	tegra_clk_clk72Mhz_8,

	tegra_clk_clk_m,

	tegra_clk_clk_m_div2,

	tegra_clk_clk_m_div4,
@@ -51,17 +53,21 @@ enum clk_id { 
	tegra_clk_cml1,

	tegra_clk_csi,

	tegra_clk_csite,

	tegra_clk_csite_8,

	tegra_clk_csus,

	tegra_clk_cve,

	tegra_clk_dam0,

	tegra_clk_dam1,

	tegra_clk_dam2,

	tegra_clk_d_audio,

	tegra_clk_dbgapb,

	tegra_clk_dds,

	tegra_clk_dfll_ref,

	tegra_clk_dfll_soc,

	tegra_clk_disp1,

	tegra_clk_disp1_8,

	tegra_clk_disp2,

	tegra_clk_disp2_8,

	tegra_clk_dp2,

	tegra_clk_dpaux,

	tegra_clk_dsialp,
@@ -71,6 +77,7 @@ enum clk_id { 
	tegra_clk_dtv,

	tegra_clk_emc,

	tegra_clk_entropy,

	tegra_clk_entropy_8,

	tegra_clk_epp,

	tegra_clk_epp_8,

	tegra_clk_extern1,
@@ -85,12 +92,16 @@ enum clk_id { 
	tegra_clk_gr3d_8,

	tegra_clk_hclk,

	tegra_clk_hda,

	tegra_clk_hda_8,

	tegra_clk_hda2codec_2x,

	tegra_clk_hda2codec_2x_8,

	tegra_clk_hda2hdmi,

	tegra_clk_hdmi,

	tegra_clk_hdmi_audio,

	tegra_clk_host1x,

	tegra_clk_host1x_8,

	tegra_clk_host1x_9,

	tegra_clk_hsic_trk,

	tegra_clk_i2c1,

	tegra_clk_i2c2,

	tegra_clk_i2c3,
@@ -110,11 +121,14 @@ enum clk_id { 
	tegra_clk_i2s4_sync,

	tegra_clk_isp,

	tegra_clk_isp_8,

	tegra_clk_isp_9,

	tegra_clk_ispb,

	tegra_clk_kbc,

	tegra_clk_kfuse,

	tegra_clk_la,

	tegra_clk_maud,

	tegra_clk_mipi,

	tegra_clk_mipibif,

	tegra_clk_mipi_cal,

	tegra_clk_mpe,

	tegra_clk_mselect,
@@ -124,15 +138,24 @@ enum clk_id { 
	tegra_clk_ndspeed,

	tegra_clk_ndspeed_8,

	tegra_clk_nor,

	tegra_clk_nvdec,

	tegra_clk_nvenc,

	tegra_clk_nvjpg,

	tegra_clk_owr,

	tegra_clk_owr_8,

	tegra_clk_pcie,

	tegra_clk_pclk,

	tegra_clk_pll_a,

	tegra_clk_pll_a_out0,

	tegra_clk_pll_a1,

	tegra_clk_pll_c,

	tegra_clk_pll_c2,

	tegra_clk_pll_c3,

	tegra_clk_pll_c4,

	tegra_clk_pll_c4_out0,

	tegra_clk_pll_c4_out1,

	tegra_clk_pll_c4_out2,

	tegra_clk_pll_c4_out3,

	tegra_clk_pll_c_out1,

	tegra_clk_pll_d,

	tegra_clk_pll_d2,
@@ -140,19 +163,29 @@ enum clk_id { 
	tegra_clk_pll_d_out0,

	tegra_clk_pll_dp,

	tegra_clk_pll_e_out0,

	tegra_clk_pll_g_ref,

	tegra_clk_pll_m,

	tegra_clk_pll_m_out1,

	tegra_clk_pll_mb,

	tegra_clk_pll_p,

	tegra_clk_pll_p_out1,

	tegra_clk_pll_p_out2,

	tegra_clk_pll_p_out2_int,

	tegra_clk_pll_p_out3,

	tegra_clk_pll_p_out4,

	tegra_clk_pll_p_out4_cpu,

	tegra_clk_pll_p_out5,

	tegra_clk_pll_p_out_hsio,

	tegra_clk_pll_p_out_xusb,

	tegra_clk_pll_p_out_cpu,

	tegra_clk_pll_p_out_adsp,

	tegra_clk_pll_ref,

	tegra_clk_pll_re_out,

	tegra_clk_pll_re_vco,

	tegra_clk_pll_u,

	tegra_clk_pll_u_out,

	tegra_clk_pll_u_out1,

	tegra_clk_pll_u_out2,

	tegra_clk_pll_u_12m,

	tegra_clk_pll_u_480m,

	tegra_clk_pll_u_48m,
@@ -160,53 +193,80 @@ enum clk_id { 
	tegra_clk_pll_x,

	tegra_clk_pll_x_out0,

	tegra_clk_pwm,

	tegra_clk_qspi,

	tegra_clk_rtc,

	tegra_clk_sata,

	tegra_clk_sata_8,

	tegra_clk_sata_cold,

	tegra_clk_sata_oob,

	tegra_clk_sata_oob_8,

	tegra_clk_sbc1,

	tegra_clk_sbc1_8,

	tegra_clk_sbc1_9,

	tegra_clk_sbc2,

	tegra_clk_sbc2_8,

	tegra_clk_sbc2_9,

	tegra_clk_sbc3,

	tegra_clk_sbc3_8,

	tegra_clk_sbc3_9,

	tegra_clk_sbc4,

	tegra_clk_sbc4_8,

	tegra_clk_sbc4_9,

	tegra_clk_sbc5,

	tegra_clk_sbc5_8,

	tegra_clk_sbc6,

	tegra_clk_sbc6_8,

	tegra_clk_sclk,

	tegra_clk_sdmmc_legacy,

	tegra_clk_sdmmc1,

	tegra_clk_sdmmc1_8,

	tegra_clk_sdmmc1_9,

	tegra_clk_sdmmc2,

	tegra_clk_sdmmc2_8,

	tegra_clk_sdmmc2_9,

	tegra_clk_sdmmc3,

	tegra_clk_sdmmc3_8,

	tegra_clk_sdmmc3_9,

	tegra_clk_sdmmc4,

	tegra_clk_sdmmc4_8,

	tegra_clk_sdmmc4_9,

	tegra_clk_se,

	tegra_clk_soc_therm,

	tegra_clk_soc_therm_8,

	tegra_clk_sor0,

	tegra_clk_sor0_lvds,

	tegra_clk_sor1,

	tegra_clk_sor1_brick,

	tegra_clk_sor1_src,

	tegra_clk_spdif,

	tegra_clk_spdif_2x,

	tegra_clk_spdif_in,

	tegra_clk_spdif_in_8,

	tegra_clk_spdif_in_sync,

	tegra_clk_spdif_mux,

	tegra_clk_spdif_out,

	tegra_clk_timer,

	tegra_clk_trace,

	tegra_clk_tsec,

	tegra_clk_tsec_8,

	tegra_clk_tsecb,

	tegra_clk_tsensor,

	tegra_clk_tvdac,

	tegra_clk_tvo,

	tegra_clk_uarta,

	tegra_clk_uarta_8,

	tegra_clk_uartb,

	tegra_clk_uartb_8,

	tegra_clk_uartc,

	tegra_clk_uartc_8,

	tegra_clk_uartd,

	tegra_clk_uartd_8,

	tegra_clk_uarte,

	tegra_clk_uarte_8,

	tegra_clk_uartape,

	tegra_clk_usb2,

	tegra_clk_usb2_hsic_trk,

	tegra_clk_usb2_trk,

	tegra_clk_usb3,

	tegra_clk_usbd,

	tegra_clk_vcp,
@@ -216,22 +276,35 @@ enum clk_id { 
	tegra_clk_vi,

	tegra_clk_vi_8,

	tegra_clk_vi_9,

	tegra_clk_vi_10,

	tegra_clk_vi_i2c,

	tegra_clk_vic03,

	tegra_clk_vic03_8,

	tegra_clk_vim2_clk,

	tegra_clk_vimclk_sync,

	tegra_clk_vi_sensor,

	tegra_clk_vi_sensor2,

	tegra_clk_vi_sensor_8,

	tegra_clk_vi_sensor_9,

	tegra_clk_vi_sensor2,

	tegra_clk_vi_sensor2_8,

	tegra_clk_xusb_dev,

	tegra_clk_xusb_dev_src,

	tegra_clk_xusb_dev_src_8,

	tegra_clk_xusb_falcon_src,

	tegra_clk_xusb_falcon_src_8,

	tegra_clk_xusb_fs_src,

	tegra_clk_xusb_gate,

	tegra_clk_xusb_host,

	tegra_clk_xusb_host_src,

	tegra_clk_xusb_host_src_8,

	tegra_clk_xusb_hs_src,

	tegra_clk_xusb_hs_src_4,

	tegra_clk_xusb_ss,

	tegra_clk_xusb_ss_src,

	tegra_clk_xusb_ss_src_8,

	tegra_clk_xusb_ss_div2,

	tegra_clk_xusb_ssp_src,

	tegra_clk_sclk_mux,

	tegra_clk_max,

};