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Commit b35f0ca7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-for-v4.14-rc7' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "Two amd fixes, one i915 core and a few i915 GVT fixes, things seem
  fairly quiet"

* tag 'drm-fixes-for-v4.14-rc7' of git://people.freedesktop.org/~airlied/linux:
  drm/i915/gvt: Adding ACTHD mmio read handler
  drm/i915/gvt: Extract mmio_read_from_hw() common function
  drm/i915/gvt: Refine MMIO_RING_F()
  drm/i915/gvt: properly check per_ctx bb valid state
  drm/i915/perf: fix perf enable/disable ioctls with 32bits userspace
  drm/amd/amdgpu: Remove workaround check for UVD6 on APUs
  drm/amd/powerplay: fix uninitialized variable
parents 5345da89 ce485df4

drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c

+5 −11
Original line number Diff line number Diff line
@@ -225,11 +225,7 @@ static int uvd_v6_0_suspend(void *handle) 
	if (r)

		return r;



	/* Skip this for APU for now */

	if (!(adev->flags & AMD_IS_APU))

		r = amdgpu_uvd_suspend(adev);



	return r;

	return amdgpu_uvd_suspend(adev);

}



static int uvd_v6_0_resume(void *handle)
@@ -237,12 +233,10 @@ static int uvd_v6_0_resume(void *handle) 
	int r;

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	/* Skip this for APU for now */

	if (!(adev->flags & AMD_IS_APU)) {

	r = amdgpu_uvd_resume(adev);

	if (r)

		return r;

	}



	return uvd_v6_0_hw_init(adev);

}

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

+3 −3
Original line number Diff line number Diff line
@@ -830,7 +830,7 @@ uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr) 
{

	uint32_t reference_clock, tmp;

	struct cgs_display_info info = {0};

	struct cgs_mode_info mode_info;

	struct cgs_mode_info mode_info = {0};



	info.mode_info = &mode_info;
@@ -3948,10 +3948,9 @@ static int smu7_program_display_gap(struct pp_hwmgr *hwmgr) 
	uint32_t ref_clock;

	uint32_t refresh_rate = 0;

	struct cgs_display_info info = {0};

	struct cgs_mode_info mode_info;

	struct cgs_mode_info mode_info = {0};



	info.mode_info = &mode_info;



	cgs_get_active_displays_info(hwmgr->device, &info);

	num_active_displays = info.display_count;
@@ -3967,6 +3966,7 @@ static int smu7_program_display_gap(struct pp_hwmgr *hwmgr) 
	frame_time_in_us = 1000000 / refresh_rate;



	pre_vbi_time_in_us = frame_time_in_us - 200 - mode_info.vblank_time_us;



	data->frame_time_x2 = frame_time_in_us * 2 / 100;



	display_gap2 = pre_vbi_time_in_us * (ref_clock / 100);

drivers/gpu/drm/i915/gvt/cmd_parser.c

+3 −0
Original line number Diff line number Diff line
@@ -2723,6 +2723,9 @@ static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 
	uint32_t per_ctx_start[CACHELINE_DWORDS] = {0};

	unsigned char *bb_start_sva;



	if (!wa_ctx->per_ctx.valid)

		return 0;



	per_ctx_start[0] = 0x18800001;

	per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;

drivers/gpu/drm/i915/gvt/execlist.c

+1 −2
Original line number Diff line number Diff line
@@ -701,8 +701,7 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id, 
			CACHELINE_BYTES;

		workload->wa_ctx.per_ctx.guest_gma =

			per_ctx & PER_CTX_ADDR_MASK;



		WARN_ON(workload->wa_ctx.indirect_ctx.size && !(per_ctx & 0x1));

		workload->wa_ctx.per_ctx.valid = per_ctx & 1;

	}



	if (emulate_schedule_in)

drivers/gpu/drm/i915/gvt/handlers.c

+10 −60
Original line number Diff line number Diff line
@@ -1429,18 +1429,7 @@ static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset, 
	return 0;

}



static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu,

		unsigned int offset, void *p_data, unsigned int bytes)

{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;



	mmio_hw_access_pre(dev_priv);

	vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));

	mmio_hw_access_post(dev_priv);

	return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);

}



static int instdone_mmio_read(struct intel_vgpu *vgpu,

static int mmio_read_from_hw(struct intel_vgpu *vgpu,

		unsigned int offset, void *p_data, unsigned int bytes)

{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
@@ -1589,6 +1578,8 @@ static int ring_reset_ctl_write(struct intel_vgpu *vgpu, 
	MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \

	MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \

	MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \

	if (HAS_BSD2(dev_priv)) \

		MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \

} while (0)



#define MMIO_RING_D(prefix, d) \
@@ -1635,10 +1626,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) 
#undef RING_REG



#define RING_REG(base) (base + 0x6c)

	MMIO_RING_DFH(RING_REG, D_ALL, 0, instdone_mmio_read, NULL);

	MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_ALL, instdone_mmio_read, NULL);

	MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);

#undef RING_REG

	MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, instdone_mmio_read, NULL);

	MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);



	MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL);

	MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);
@@ -1648,7 +1638,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) 
	MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);

	MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);

	MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);

	MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, NULL, NULL);

	MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, mmio_read_from_hw, NULL);

	MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);



	/* RING MODE */
@@ -1662,9 +1652,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) 
	MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,

			NULL, NULL);

	MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,

			ring_timestamp_mmio_read, NULL);

			mmio_read_from_hw, NULL);

	MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,

			ring_timestamp_mmio_read, NULL);

			mmio_read_from_hw, NULL);



	MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
@@ -2411,9 +2401,6 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt) 
	struct drm_i915_private *dev_priv = gvt->dev_priv;

	int ret;



	MMIO_DFH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, NULL,

			intel_vgpu_reg_imr_handler);



	MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);

	MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);

	MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
@@ -2476,68 +2463,34 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt) 
	MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,

		intel_vgpu_reg_master_irq_handler);



	MMIO_DFH(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS,

		F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x1c134, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);



	MMIO_DFH(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,

		NULL, NULL);

	MMIO_DFH(RING_HEAD(GEN8_BSD2_RING_BASE),  D_BDW_PLUS,

		F_CMD_ACCESS, NULL, NULL);

	MMIO_GM_RDR(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL);

	MMIO_DFH(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,

		NULL, NULL);

	MMIO_DFH(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS,

		F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS,

		F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,

		ring_mode_mmio_write);

	MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS,

		F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS,

		F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,

			ring_timestamp_mmio_read, NULL);



	MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS,

		mmio_read_from_hw, NULL);



#define RING_REG(base) (base + 0xd0)

	MMIO_RING_F(RING_REG, 4, F_RO, 0,

		~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,

		ring_reset_ctl_write);

	MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0,

		~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,

		ring_reset_ctl_write);

#undef RING_REG



#define RING_REG(base) (base + 0x230)

	MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);

	MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write);

#undef RING_REG



#define RING_REG(base) (base + 0x234)

	MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,

		NULL, NULL);

	MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO | F_CMD_ACCESS, 0,

		~0LL, D_BDW_PLUS, NULL, NULL);

#undef RING_REG



#define RING_REG(base) (base + 0x244)

	MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,

		NULL, NULL);

#undef RING_REG



#define RING_REG(base) (base + 0x370)

	MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);

	MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS,

			NULL, NULL);

#undef RING_REG



#define RING_REG(base) (base + 0x3a0)

	MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);

	MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL);

#undef RING_REG



	MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
@@ -2557,11 +2510,9 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt) 


#define RING_REG(base) (base + 0x270)

	MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);

	MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);

#undef RING_REG



	MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL);

	MMIO_GM_RDR(RING_HWS_PGA(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL);



	MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
@@ -2849,7 +2800,6 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) 
	MMIO_D(0x65f08, D_SKL | D_KBL);

	MMIO_D(0x320f0, D_SKL | D_KBL);



	MMIO_DFH(_REG_VCS2_EXCC, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);

	MMIO_D(0x70034, D_SKL_PLUS);

	MMIO_D(0x71034, D_SKL_PLUS);

	MMIO_D(0x72034, D_SKL_PLUS);