Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b2e8c6cd authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Streamline gpio_mmio_base deduction 



If we ignore the BXT situation, we can observe that the only variables
affecting gpio_mmio_base is IS_VALLEVIEW and HAS_GMCH_DISPLAY. The BXT
situation we can fit into the same pattern if we change gmbus_pins_bxt[]
to house the GMCH GPIO register offsets (like we do for all other
platfotms). So let's do that.

We could even simplify the VLV situation more by including the
display_mmio_offset in the GPIO register defines, but let's leave it be
for now.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446672017-24497-13-git-send-email-ville.syrjala@linux.intel.com


Reviewed-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 78e0d2e3

drivers/gpu/drm/i915/intel_i2c.c

+7 −8
Original line number Diff line number Diff line
@@ -63,9 +63,9 @@ static const struct gmbus_pin gmbus_pins_skl[] = { 
};



static const struct gmbus_pin gmbus_pins_bxt[] = {

	[GMBUS_PIN_1_BXT] = { "dpb", PCH_GPIOB },

	[GMBUS_PIN_2_BXT] = { "dpc", PCH_GPIOC },

	[GMBUS_PIN_3_BXT] = { "misc", PCH_GPIOD },

	[GMBUS_PIN_1_BXT] = { "dpb", GPIOB },

	[GMBUS_PIN_2_BXT] = { "dpc", GPIOC },

	[GMBUS_PIN_3_BXT] = { "misc", GPIOD },

};



/* pin is expected to be valid */
@@ -628,12 +628,11 @@ int intel_setup_gmbus(struct drm_device *dev) 


	if (HAS_PCH_NOP(dev))

		return 0;

	else if (HAS_PCH_SPLIT(dev))

		dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;

	else if (IS_VALLEYVIEW(dev))



	if (IS_VALLEYVIEW(dev))

		dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;

	else

		dev_priv->gpio_mmio_base = 0;

	else if (!HAS_GMCH_DISPLAY(dev))

		dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;



	mutex_init(&dev_priv->gmbus_mutex);

	init_waitqueue_head(&dev_priv->gmbus_wait_queue);