Loading Documentation/clk.txt +2 −25 Original line number Diff line number Diff line Loading @@ -230,30 +230,7 @@ clk_register(...) See the basic clock types in drivers/clk/clk-*.c for examples. Part 5 - static initialization of clock data For platforms with many clocks (often numbering into the hundreds) it may be desirable to statically initialize some clock data. This presents a problem since the definition of struct clk should be hidden from everyone except for the clock core in drivers/clk/clk.c. To get around this problem struct clk's definition is exposed in include/linux/clk-private.h along with some macros for more easily initializing instances of the basic clock types. These clocks must still be initialized with the common clock framework via a call to __clk_init. clk-private.h must NEVER be included by code which implements struct clk_ops callbacks, nor must it be included by any logic which pokes around inside of struct clk at run-time. To do so is a layering violation. To better enforce this policy, always follow this simple rule: any statically initialized clock data MUST be defined in a separate file from the logic that implements its ops. Basically separate the logic from the data and all is well. Part 6 - Disabling clock gating of unused clocks Part 5 - Disabling clock gating of unused clocks Sometimes during development it can be useful to be able to bypass the default disabling of unused clocks. For example, if drivers aren't enabling Loading @@ -264,7 +241,7 @@ are sorted out. To bypass this disabling, include "clk_ignore_unused" in the bootargs to the kernel. Part 7 - Locking Part 6 - Locking The common clock framework uses two global locks, the prepare lock and the enable lock. Loading Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt 0 → 100644 +23 −0 Original line number Diff line number Diff line Mediatek apmixedsys controller ============================== The Mediatek apmixedsys controller provides the PLLs to the system. Required Properties: - compatible: Should be: - "mediatek,mt8135-apmixedsys" - "mediatek,mt8173-apmixedsys" - #clock-cells: Must be 1 The apmixedsys controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt The available clocks are defined in dt-bindings/clock/mt*-clk.h. Example: apmixedsys: clock-controller@10209000 { compatible = "mediatek,mt8173-apmixedsys"; reg = <0 0x10209000 0 0x1000>; #clock-cells = <1>; }; Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt 0 → 100644 +30 −0 Original line number Diff line number Diff line Mediatek infracfg controller ============================ The Mediatek infracfg controller provides various clocks and reset outputs to the system. Required Properties: - compatible: Should be: - "mediatek,mt8135-infracfg", "syscon" - "mediatek,mt8173-infracfg", "syscon" - #clock-cells: Must be 1 - #reset-cells: Must be 1 The infracfg controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt The available clocks are defined in dt-bindings/clock/mt*-clk.h. Also it uses the common reset controller binding from Documentation/devicetree/bindings/reset/reset.txt. The available reset outputs are defined in dt-bindings/reset-controller/mt*-resets.h Example: infracfg: power-controller@10001000 { compatible = "mediatek,mt8173-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt 0 → 100644 +30 −0 Original line number Diff line number Diff line Mediatek pericfg controller =========================== The Mediatek pericfg controller provides various clocks and reset outputs to the system. Required Properties: - compatible: Should be: - "mediatek,mt8135-pericfg", "syscon" - "mediatek,mt8173-pericfg", "syscon" - #clock-cells: Must be 1 - #reset-cells: Must be 1 The pericfg controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt The available clocks are defined in dt-bindings/clock/mt*-clk.h. Also it uses the common reset controller binding from Documentation/devicetree/bindings/reset/reset.txt. The available reset outputs are defined in dt-bindings/reset-controller/mt*-resets.h Example: pericfg: power-controller@10003000 { compatible = "mediatek,mt8173-pericfg", "syscon"; reg = <0 0x10003000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt 0 → 100644 +23 −0 Original line number Diff line number Diff line Mediatek topckgen controller ============================ The Mediatek topckgen controller provides various clocks to the system. Required Properties: - compatible: Should be: - "mediatek,mt8135-topckgen" - "mediatek,mt8173-topckgen" - #clock-cells: Must be 1 The topckgen controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt The available clocks are defined in dt-bindings/clock/mt*-clk.h. Example: topckgen: power-controller@10000000 { compatible = "mediatek,mt8173-topckgen"; reg = <0 0x10000000 0 0x1000>; #clock-cells = <1>; }; Loading
Documentation/clk.txt +2 −25 Original line number Diff line number Diff line Loading @@ -230,30 +230,7 @@ clk_register(...) See the basic clock types in drivers/clk/clk-*.c for examples. Part 5 - static initialization of clock data For platforms with many clocks (often numbering into the hundreds) it may be desirable to statically initialize some clock data. This presents a problem since the definition of struct clk should be hidden from everyone except for the clock core in drivers/clk/clk.c. To get around this problem struct clk's definition is exposed in include/linux/clk-private.h along with some macros for more easily initializing instances of the basic clock types. These clocks must still be initialized with the common clock framework via a call to __clk_init. clk-private.h must NEVER be included by code which implements struct clk_ops callbacks, nor must it be included by any logic which pokes around inside of struct clk at run-time. To do so is a layering violation. To better enforce this policy, always follow this simple rule: any statically initialized clock data MUST be defined in a separate file from the logic that implements its ops. Basically separate the logic from the data and all is well. Part 6 - Disabling clock gating of unused clocks Part 5 - Disabling clock gating of unused clocks Sometimes during development it can be useful to be able to bypass the default disabling of unused clocks. For example, if drivers aren't enabling Loading @@ -264,7 +241,7 @@ are sorted out. To bypass this disabling, include "clk_ignore_unused" in the bootargs to the kernel. Part 7 - Locking Part 6 - Locking The common clock framework uses two global locks, the prepare lock and the enable lock. Loading
Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt 0 → 100644 +23 −0 Original line number Diff line number Diff line Mediatek apmixedsys controller ============================== The Mediatek apmixedsys controller provides the PLLs to the system. Required Properties: - compatible: Should be: - "mediatek,mt8135-apmixedsys" - "mediatek,mt8173-apmixedsys" - #clock-cells: Must be 1 The apmixedsys controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt The available clocks are defined in dt-bindings/clock/mt*-clk.h. Example: apmixedsys: clock-controller@10209000 { compatible = "mediatek,mt8173-apmixedsys"; reg = <0 0x10209000 0 0x1000>; #clock-cells = <1>; };
Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt 0 → 100644 +30 −0 Original line number Diff line number Diff line Mediatek infracfg controller ============================ The Mediatek infracfg controller provides various clocks and reset outputs to the system. Required Properties: - compatible: Should be: - "mediatek,mt8135-infracfg", "syscon" - "mediatek,mt8173-infracfg", "syscon" - #clock-cells: Must be 1 - #reset-cells: Must be 1 The infracfg controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt The available clocks are defined in dt-bindings/clock/mt*-clk.h. Also it uses the common reset controller binding from Documentation/devicetree/bindings/reset/reset.txt. The available reset outputs are defined in dt-bindings/reset-controller/mt*-resets.h Example: infracfg: power-controller@10001000 { compatible = "mediatek,mt8173-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; };
Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt 0 → 100644 +30 −0 Original line number Diff line number Diff line Mediatek pericfg controller =========================== The Mediatek pericfg controller provides various clocks and reset outputs to the system. Required Properties: - compatible: Should be: - "mediatek,mt8135-pericfg", "syscon" - "mediatek,mt8173-pericfg", "syscon" - #clock-cells: Must be 1 - #reset-cells: Must be 1 The pericfg controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt The available clocks are defined in dt-bindings/clock/mt*-clk.h. Also it uses the common reset controller binding from Documentation/devicetree/bindings/reset/reset.txt. The available reset outputs are defined in dt-bindings/reset-controller/mt*-resets.h Example: pericfg: power-controller@10003000 { compatible = "mediatek,mt8173-pericfg", "syscon"; reg = <0 0x10003000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; };
Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt 0 → 100644 +23 −0 Original line number Diff line number Diff line Mediatek topckgen controller ============================ The Mediatek topckgen controller provides various clocks to the system. Required Properties: - compatible: Should be: - "mediatek,mt8135-topckgen" - "mediatek,mt8173-topckgen" - #clock-cells: Must be 1 The topckgen controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt The available clocks are defined in dt-bindings/clock/mt*-clk.h. Example: topckgen: power-controller@10000000 { compatible = "mediatek,mt8173-topckgen"; reg = <0 0x10000000 0 0x1000>; #clock-cells = <1>; };