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Commit b27aef49 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 4.19.235 into android-4.19-stable 



Changes in 4.19.235
	net: qlogic: check the return value of dma_alloc_coherent() in qed_vf_hw_prepare()
	qed: return status of qed_iov_get_link
	ethernet: Fix error handling in xemaclite_of_probe
	net: ethernet: ti: cpts: Handle error for clk_enable
	net: ethernet: lpc_eth: Handle error for clk_enable
	ax25: Fix NULL pointer dereference in ax25_kill_by_device
	net/mlx5: Fix size field in bufferx_reg struct
	NFC: port100: fix use-after-free in port100_send_complete
	gpio: ts4900: Do not set DAT and OE together
	gianfar: ethtool: Fix refcount leak in gfar_get_ts_info
	net: phy: DP83822: clear MISR2 register to disable interrupts
	sctp: fix kernel-infoleak for SCTP sockets
	net-sysfs: add check for netdevice being present to speed_show
	Revert "xen-netback: remove 'hotplug-status' once it has served its purpose"
	Revert "xen-netback: Check for hotplug-status existence before watching"
	tracing: Ensure trace buffer is at least 4096 bytes large
	selftests/memfd: clean up mapping in mfd_fail_write
	ARM: Spectre-BHB: provide empty stub for non-config
	staging: gdm724x: fix use after free in gdm_lte_rx()
	net: macb: Fix lost RX packet wakeup race in NAPI receive
	riscv: Fix auipc+jalr relocation range checks
	virtio: unexport virtio_finalize_features
	virtio: acknowledge all features before access
	ARM: fix Thumb2 regression with Spectre BHB
	ext4: add check to prevent attempting to resize an fs with sparse_super2
	btrfs: unlock newly allocated extent buffer after error
	Linux 4.19.235

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@google.com>
Change-Id: I24b49e6096aa8f0f7d0d5136da911da90c8b5da7
parents 5b194414 6b481672

Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

VERSION = 4

PATCHLEVEL = 19

SUBLEVEL = 234

SUBLEVEL = 235

EXTRAVERSION =

NAME = "People's Front"

arch/arm/include/asm/spectre.h

+6 −0
Original line number Diff line number Diff line
@@ -25,7 +25,13 @@ enum { 
	SPECTRE_V2_METHOD_LOOP8 = BIT(__SPECTRE_V2_METHOD_LOOP8),

};



#ifdef CONFIG_GENERIC_CPU_VULNERABILITIES

void spectre_v2_update_state(unsigned int state, unsigned int methods);

#else

static inline void spectre_v2_update_state(unsigned int state,

					   unsigned int methods)

{}

#endif



int spectre_bhb_update_vectors(unsigned int method);

arch/arm/kernel/entry-armv.S

+2 −2
Original line number Diff line number Diff line
@@ -1067,9 +1067,9 @@ vector_bhb_loop8_\name: 


	@ bhb workaround

	mov	r0, #8

1:	b	. + 4

3:	b	. + 4

	subs	r0, r0, #1

	bne	1b

	bne	3b

	dsb

	isb

	b	2b

arch/riscv/kernel/module.c

+16 −5
Original line number Diff line number Diff line
@@ -21,6 +21,19 @@ 
#include <asm/pgtable.h>

#include <asm/sections.h>



/*

 * The auipc+jalr instruction pair can reach any PC-relative offset

 * in the range [-2^31 - 2^11, 2^31 - 2^11)

 */

static bool riscv_insn_valid_32bit_offset(ptrdiff_t val)

{

#ifdef CONFIG_32BIT

	return true;

#else

	return (-(1L << 31) - (1L << 11)) <= val && val < ((1L << 31) - (1L << 11));

#endif

}



static int apply_r_riscv_32_rela(struct module *me, u32 *location, Elf_Addr v)

{

	if (v != (u32)v) {
@@ -103,7 +116,7 @@ static int apply_r_riscv_pcrel_hi20_rela(struct module *me, u32 *location, 
	ptrdiff_t offset = (void *)v - (void *)location;

	s32 hi20;



	if (offset != (s32)offset) {

	if (!riscv_insn_valid_32bit_offset(offset)) {

		pr_err(

		  "%s: target %016llx can not be addressed by the 32-bit offset from PC = %p\n",

		  me->name, (long long)v, location);
@@ -205,10 +218,9 @@ static int apply_r_riscv_call_plt_rela(struct module *me, u32 *location, 
				       Elf_Addr v)

{

	ptrdiff_t offset = (void *)v - (void *)location;

	s32 fill_v = offset;

	u32 hi20, lo12;



	if (offset != fill_v) {

	if (!riscv_insn_valid_32bit_offset(offset)) {

		/* Only emit the plt entry if offset over 32-bit range */

		if (IS_ENABLED(CONFIG_MODULE_SECTIONS)) {

			offset = module_emit_plt_entry(me, v);
@@ -232,10 +244,9 @@ static int apply_r_riscv_call_rela(struct module *me, u32 *location, 
				   Elf_Addr v)

{

	ptrdiff_t offset = (void *)v - (void *)location;

	s32 fill_v = offset;

	u32 hi20, lo12;



	if (offset != fill_v) {

	if (!riscv_insn_valid_32bit_offset(offset)) {

		pr_err(

		  "%s: target %016llx can not be addressed by the 32-bit offset from PC = %p\n",

		  me->name, (long long)v, location);

drivers/gpio/gpio-ts4900.c

+19 −5
Original line number Diff line number Diff line 
/*

 * Digital I/O driver for Technologic Systems I2C FPGA Core

 *

 * Copyright (C) 2015 Technologic Systems

 * Copyright (C) 2015, 2018 Technologic Systems

 * Copyright (C) 2016 Savoir-Faire Linux

 *

 * This program is free software; you can redistribute it and/or
@@ -52,19 +52,33 @@ static int ts4900_gpio_direction_input(struct gpio_chip *chip, 
{

	struct ts4900_gpio_priv *priv = gpiochip_get_data(chip);



	/*

	 * This will clear the output enable bit, the other bits are

	 * dontcare when this is cleared

	/* Only clear the OE bit here, requires a RMW. Prevents potential issue

	 * with OE and data getting to the physical pin at different times.

	 */

	return regmap_write(priv->regmap, offset, 0);

	return regmap_update_bits(priv->regmap, offset, TS4900_GPIO_OE, 0);

}



static int ts4900_gpio_direction_output(struct gpio_chip *chip,

					unsigned int offset, int value)

{

	struct ts4900_gpio_priv *priv = gpiochip_get_data(chip);

	unsigned int reg;

	int ret;



	/* If changing from an input to an output, we need to first set the

	 * proper data bit to what is requested and then set OE bit. This

	 * prevents a glitch that can occur on the IO line

	 */

	regmap_read(priv->regmap, offset, &reg);

	if (!(reg & TS4900_GPIO_OE)) {

		if (value)

			reg = TS4900_GPIO_OUT;

		else

			reg &= ~TS4900_GPIO_OUT;



		regmap_write(priv->regmap, offset, reg);

	}



	if (value)

		ret = regmap_write(priv->regmap, offset, TS4900_GPIO_OE |

							 TS4900_GPIO_OUT);