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Commit b2762686 authored by Andi Kleen's avatar Andi Kleen Committed by H. Peter Anvin
Browse files

x86, mce, cmci: factor out threshold interrupt handler 



Impact: cleanup; preparation for feature

The mce_amd_64 code has an own private MC threshold vector with an own
interrupt handler. Since Intel needs a similar handler
it makes sense to share the vector because both can not
be active at the same time.

I factored the common APIC handler code into a separate file which can
be used by both the Intel or AMD MC code.

This is needed for the next patch which adds an Intel specific
CMCI handler.

This patch should be a nop for AMD, it just moves some code
around.

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Signed-off-by: default avatarH. Peter Anvin <hpa@zytor.com>
parent 41fdff32

arch/x86/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -751,6 +751,11 @@ config X86_MCE_AMD 
	   Additional support for AMD specific MCE features such as

	   the DRAM Error Threshold.



config X86_MCE_THRESHOLD

	depends on X86_MCE_AMD || X86_MCE_INTEL

	bool

	default y



config X86_MCE_NONFATAL

	tristate "Check for non-fatal errors on AMD Athlon/Duron / Intel Pentium 4"

	depends on X86_32 && X86_MCE

arch/x86/include/asm/mce.h

+2 −0
Original line number Diff line number Diff line
@@ -135,5 +135,7 @@ extern void mcheck_init(struct cpuinfo_x86 *c); 
#define mcheck_init(c) do { } while (0)

#endif



extern void (*mce_threshold_vector)(void);



#endif /* __KERNEL__ */

#endif /* _ASM_X86_MCE_H */

arch/x86/kernel/cpu/mcheck/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -4,3 +4,4 @@ obj-$(CONFIG_X86_32) += k7.o p4.o p5.o p6.o winchip.o 
obj-$(CONFIG_X86_MCE_INTEL)	+= mce_intel_64.o

obj-$(CONFIG_X86_MCE_AMD)	+= mce_amd_64.o

obj-$(CONFIG_X86_MCE_NONFATAL)	+= non-fatal.o

obj-$(CONFIG_X86_MCE_THRESHOLD) += threshold.o

arch/x86/kernel/cpu/mcheck/mce_amd_64.c

+6 −9
Original line number Diff line number Diff line
@@ -79,6 +79,8 @@ static unsigned char shared_bank[NR_BANKS] = { 


static DEFINE_PER_CPU(unsigned char, bank_map);	/* see which banks are on */



static void amd_threshold_interrupt(void);



/*

 * CPU Initialization

 */
@@ -174,6 +176,8 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) 
			tr.reset = 0;

			tr.old_limit = 0;

			threshold_restart_bank(&tr);



			mce_threshold_vector = amd_threshold_interrupt;

		}

	}

}
@@ -187,16 +191,12 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) 
 * the interrupt goes off when error_count reaches threshold_limit.

 * the handler will simply log mcelog w/ software defined bank number.

 */

asmlinkage void mce_threshold_interrupt(void)

static void amd_threshold_interrupt(void)

{

	unsigned int bank, block;

	struct mce m;

	u32 low = 0, high = 0, address = 0;



	ack_APIC_irq();

	exit_idle();

	irq_enter();



	mce_setup(&m);



	/* assume first bank caused it */
@@ -241,13 +241,10 @@ asmlinkage void mce_threshold_interrupt(void) 
				       + bank * NR_BLOCKS

				       + block;

				mce_log(&m);

				goto out;

				return;

			}

		}

	}

out:

	inc_irq_stat(irq_threshold_count);

	irq_exit();

}



/*

arch/x86/kernel/cpu/mcheck/threshold.c

0 → 100644
+24 −0
Original line number Diff line number Diff line 
/* Common corrected MCE threshold handler code */

#include <linux/kernel.h>

#include <linux/interrupt.h>

#include <asm/mce.h>

#include <asm/irq_vectors.h>

#include <asm/idle.h>



static void default_threshold_interrupt(void)

{

	printk(KERN_ERR "Unexpected threshold interrupt at vector %x\n",

			 THRESHOLD_APIC_VECTOR);

}



void (*mce_threshold_vector)(void) = default_threshold_interrupt;



asmlinkage void mce_threshold_interrupt(void)

{

	ack_APIC_irq();

	exit_idle();

	irq_enter();

	inc_irq_stat(irq_threshold_count);

	mce_threshold_vector();

	irq_exit();

}