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Commit b258e09d authored by Aditya Bavanari's avatar Aditya Bavanari Committed by Gerrit - the friendly Code Review server
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asoc: codecs: Update muxsel registers only when clock counts are not stale 



During SSR/PDR use cases, core clock count in different
macros becomes stale and muxsel registers are accessed
leading to NOC errors. Update muxsel registers only after
clock counts are reset after SSR/PDR recovery.

Change-Id: I656f8e7ddc8a92a325c2ba644f1a945cbafb08a0
Signed-off-by: default avatarAditya Bavanari <abavanar@codeaurora.org>
parent 4e8e51f8

asoc/codecs/bolero/bolero-cdc.c

+4 −0
Original line number Diff line number Diff line
@@ -828,6 +828,10 @@ static int bolero_ssr_enable(struct device *dev, void *data) 
				priv->component,

				BOLERO_MACRO_EVT_CLK_RESET, 0x0);

	}



	if (priv->rsc_clk_cb)

		priv->rsc_clk_cb(priv->clk_dev, BOLERO_MACRO_EVT_SSR_GFMUX_UP);



	trace_printk("%s: clk count reset\n", __func__);

	regcache_cache_only(priv->regmap, false);

	mutex_lock(&priv->clk_lock);

asoc/codecs/bolero/bolero-cdc.h

+2 −1
Original line number Diff line number Diff line
@@ -52,7 +52,8 @@ enum { 
	BOLERO_MACRO_EVT_CLK_RESET,

	BOLERO_MACRO_EVT_REG_WAKE_IRQ,

	BOLERO_MACRO_EVT_RX_COMPANDER_SOFT_RST,

	BOLERO_MACRO_EVT_BCS_CLK_OFF

	BOLERO_MACRO_EVT_BCS_CLK_OFF,

	BOLERO_MACRO_EVT_SSR_GFMUX_UP,

};



enum {

asoc/codecs/bolero/bolero-clk-rsc.c

+20 −10
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ struct bolero_clk_rsc { 
	int reg_seq_en_cnt;

	int va_tx_clk_cnt;

	bool dev_up;

	bool dev_up_gfmux;

	u32 num_fs_reg;

	u32 *fs_gen_seq;

	int default_clk_id[MAX_CLK];
@@ -65,10 +66,14 @@ static int bolero_clk_rsc_cb(struct device *dev, u16 event) 
	}



	mutex_lock(&priv->rsc_clk_lock);

	if (event == BOLERO_MACRO_EVT_SSR_UP)

	if (event == BOLERO_MACRO_EVT_SSR_UP) {

		priv->dev_up = true;

	else if (event == BOLERO_MACRO_EVT_SSR_DOWN)

	} else if (event == BOLERO_MACRO_EVT_SSR_DOWN) {

		priv->dev_up = false;

		priv->dev_up_gfmux = false;

	} else if (event == BOLERO_MACRO_EVT_SSR_GFMUX_UP) {

		priv->dev_up_gfmux = true;

	}

	mutex_unlock(&priv->rsc_clk_lock);



	return 0;
@@ -282,10 +287,12 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv, 
			 * care in DSP itself

			 */

			if (clk_id != VA_CORE_CLK) {

				if (priv->dev_up_gfmux) {

					iowrite32(0x1, clk_muxsel);

					muxsel = ioread32(clk_muxsel);

					trace_printk("%s: muxsel value after enable: %d\n",

							__func__, muxsel);

				}

				bolero_clk_rsc_mux0_clk_request(priv,

							default_clk_id,

							false);
@@ -313,12 +320,14 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv, 
					 * This configuration would be taken

					 * care in DSP itself.

					 */

					if (priv->dev_up_gfmux) {

						iowrite32(0x0, clk_muxsel);

						muxsel = ioread32(clk_muxsel);

						trace_printk("%s: muxsel value after disable: %d\n",

								__func__, muxsel);

					}

				}

			}

			if (priv->clk[clk_id + NPL_CLK_OFFSET])

				clk_disable_unprepare(

					priv->clk[clk_id + NPL_CLK_OFFSET]);
@@ -706,6 +715,7 @@ static int bolero_clk_rsc_probe(struct platform_device *pdev) 
	}

	priv->dev = &pdev->dev;

	priv->dev_up = true;

	priv->dev_up_gfmux = true;

	mutex_init(&priv->rsc_clk_lock);

	mutex_init(&priv->fs_gen_lock);

	dev_set_drvdata(&pdev->dev, priv);