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Commit b18c1bb4 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Remove 64b mmio write vfuncs 



We don't have safe 64-bit mmio writes as they are really split into
2x32-bit writes. This tearing is dangerous as the hardware *will*
operate on the intermediate value, requiring great care when assigning.
(See, for example, i965_write_fence_reg.) As such we don't currently use
them and strongly advise not to us them. Go one step further and remove
the 64-bit write vfuncs.

v2: Add some more details to the comment about why WRITE64 is absent,
and why you need to think twice before using READ64.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20160906144538.4204-1-chris@chris-wilson.co.uk
parent e320d400

drivers/gpu/drm/i915/i915_drv.h

+9 −4
Original line number Diff line number Diff line
@@ -579,8 +579,6 @@ struct intel_uncore_funcs { 
				uint16_t val, bool trace);

	void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,

				uint32_t val, bool trace);

	void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,

				uint64_t val, bool trace);

};



struct intel_uncore {
@@ -3758,9 +3756,16 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); 
 * will be implemented using 2 32-bit writes in an arbitrary order with

 * an arbitrary delay between them. This can cause the hardware to

 * act upon the intermediate value, possibly leading to corruption and

 * machine death. You have been warned.

 * machine death. For this reason we do not support I915_WRITE64, or

 * dev_priv->uncore.funcs.mmio_writeq.

 *

 * When reading a 64-bit value as two 32-bit values, the delay may cause

 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that

 * occasionally a 64-bit register does not actualy support a full readq

 * and must be read using two 32-bit reads.

 *

 * You have been warned.

 */

#define I915_WRITE64(reg, val)	dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)

#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)



#define I915_READ64_2x32(lower_reg, upper_reg) ({			\

drivers/gpu/drm/i915/intel_uncore.c

+0 −9
Original line number Diff line number Diff line
@@ -1018,11 +1018,9 @@ gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool 
__gen5_write(8)

__gen5_write(16)

__gen5_write(32)

__gen5_write(64)

__gen2_write(8)

__gen2_write(16)

__gen2_write(32)

__gen2_write(64)



#undef __gen5_write

#undef __gen2_write
@@ -1112,23 +1110,18 @@ gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \ 
__gen9_write(8)

__gen9_write(16)

__gen9_write(32)

__gen9_write(64)

__chv_write(8)

__chv_write(16)

__chv_write(32)

__chv_write(64)

__gen8_write(8)

__gen8_write(16)

__gen8_write(32)

__gen8_write(64)

__hsw_write(8)

__hsw_write(16)

__hsw_write(32)

__hsw_write(64)

__gen6_write(8)

__gen6_write(16)

__gen6_write(32)

__gen6_write(64)



#undef __gen9_write

#undef __chv_write
@@ -1158,7 +1151,6 @@ static void vgpu_write##x(struct drm_i915_private *dev_priv, \ 
__vgpu_write(8)

__vgpu_write(16)

__vgpu_write(32)

__vgpu_write(64)



#undef __vgpu_write

#undef VGPU_WRITE_FOOTER
@@ -1169,7 +1161,6 @@ do { \ 
	dev_priv->uncore.funcs.mmio_writeb = x##_write8; \

	dev_priv->uncore.funcs.mmio_writew = x##_write16; \

	dev_priv->uncore.funcs.mmio_writel = x##_write32; \

	dev_priv->uncore.funcs.mmio_writeq = x##_write64; \

} while (0)



#define ASSIGN_READ_MMIO_VFUNCS(x) \