ARM: 5978/1: plat-nomadik: use one-shot clock events (b102c01f) · Commits · e / devices / android_kernel_oneplus_sm7250

arch/arm/plat-nomadik/timer.c

+63 −62

Original line number	Original line	Diff line number	Diff line
	@@ -2,7 +2,7 @@
	* linux/arch/arm/mach-nomadik/timer.c		* linux/arch/arm/mach-nomadik/timer.c
	*		*
	* Copyright (C) 2008 STMicroelectronics		* Copyright (C) 2008 STMicroelectronics
	* Copyright (C) 2009 Alessandro Rubini, somewhat based on at91sam926x		* Copyright (C) 2010 Alessandro Rubini
	*		*
	* This program is free software; you can redistribute it and/or modify		* This program is free software; you can redistribute it and/or modify
	* it under the terms of the GNU General Public License version 2, as		* it under the terms of the GNU General Public License version 2, as
	@@ -18,123 +18,124 @@

	#include <plat/mtu.h>		#include <plat/mtu.h>

	static u32 nmdk_count; /* accumulated count */		void __iomem mtu_base; / ssigned by machine code */
	static u32 nmdk_cycle; /* write-once */

	/* setup by the platform code */		/* clocksource: MTU decrements, so we negate the value being read. */
	void __iomem *mtu_base;

	/*
	* clocksource: the MTU device is a decrementing counters, so we negate
	* the value being read.
	*/
	static cycle_t nmdk_read_timer(struct clocksource *cs)		static cycle_t nmdk_read_timer(struct clocksource *cs)
	{		{
	u32 count = readl(mtu_base + MTU_VAL(0));		return -readl(mtu_base + MTU_VAL(0));
	return nmdk_count + nmdk_cycle - count;

	}		}

	static struct clocksource nmdk_clksrc = {		static struct clocksource nmdk_clksrc = {
	.name = "mtu_0",		.name = "mtu_0",
	.rating = 120,		.rating = 200,
	.read = nmdk_read_timer,		.read = nmdk_read_timer,
			.mask = CLOCKSOURCE_MASK(32),
	.shift = 20,		.shift = 20,
	.flags = CLOCK_SOURCE_IS_CONTINUOUS,		.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	};		};

	/*		/* Clockevent device: use one-shot mode */
	* Clockevent device: currently only periodic mode is supported
	*/
	static void nmdk_clkevt_mode(enum clock_event_mode mode,		static void nmdk_clkevt_mode(enum clock_event_mode mode,
	struct clock_event_device *dev)		struct clock_event_device *dev)
	{		{
			u32 cr;

	switch (mode) {		switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:		case CLOCK_EVT_MODE_PERIODIC:
	/* count current value? */		pr_err("%s: periodic mode not supported\n", __func__);
	writel(readl(mtu_base + MTU_IMSC) \| 1, mtu_base + MTU_IMSC);
	break;		break;
	case CLOCK_EVT_MODE_ONESHOT:		case CLOCK_EVT_MODE_ONESHOT:
	BUG(); /* Not supported, yet */		/* Load highest value, enable device, enable interrupts */
	/* FALLTHROUGH */		cr = readl(mtu_base + MTU_CR(1));
			writel(0, mtu_base + MTU_LR(1));
			writel(cr \| MTU_CRn_ENA, mtu_base + MTU_CR(1));
			writel(0x2, mtu_base + MTU_IMSC);
			break;
	case CLOCK_EVT_MODE_SHUTDOWN:		case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:		case CLOCK_EVT_MODE_UNUSED:
	writel(readl(mtu_base + MTU_IMSC) & ~1, mtu_base + MTU_IMSC);		/* disable irq */
			writel(0, mtu_base + MTU_IMSC);
	break;		break;
	case CLOCK_EVT_MODE_RESUME:		case CLOCK_EVT_MODE_RESUME:
	break;		break;
	}		}
	}		}

			static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
			{
			/* writing the value has immediate effect */
			writel(evt, mtu_base + MTU_LR(1));
			return 0;
			}

	static struct clock_event_device nmdk_clkevt = {		static struct clock_event_device nmdk_clkevt = {
	.name = "mtu_0",		.name = "mtu_1",
	.features = CLOCK_EVT_FEAT_PERIODIC,		.features = CLOCK_EVT_FEAT_ONESHOT,
	.shift = 32,		.shift = 32,
	.rating = 100,		.rating = 200,
	.set_mode = nmdk_clkevt_mode,		.set_mode = nmdk_clkevt_mode,
			.set_next_event = nmdk_clkevt_next,
	};		};

	/*		/*
	* IRQ Handler for the timer 0 of the MTU block. The irq is not shared		* IRQ Handler for timer 1 of the MTU block.
	* as we are the only users of mtu0 by now.
	*/		*/
	static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)		static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
	{		{
	/* ack: "interrupt clear register" */		struct clock_event_device *evdev = dev_id;
	writel(1 << 0, mtu_base + MTU_ICR);

	/* we can't count lost ticks, unfortunately */
	nmdk_count += nmdk_cycle;
	nmdk_clkevt.event_handler(&nmdk_clkevt);

			writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
			evdev->event_handler(evdev);
	return IRQ_HANDLED;		return IRQ_HANDLED;
	}		}

	/*
	* Set up timer interrupt, and return the current time in seconds.
	*/
	static struct irqaction nmdk_timer_irq = {		static struct irqaction nmdk_timer_irq = {
	.name = "Nomadik Timer Tick",		.name = "Nomadik Timer Tick",
	.flags = IRQF_DISABLED \| IRQF_TIMER,		.flags = IRQF_DISABLED \| IRQF_TIMER,
	.handler = nmdk_timer_interrupt,		.handler = nmdk_timer_interrupt,
			.dev_id = &nmdk_clkevt,
	};		};

	static void nmdk_timer_reset(void)
	{
	u32 cr;

	writel(0, mtu_base + MTU_CR(0)); /* off */

	/* configure load and background-load, and fire it up */
	writel(nmdk_cycle, mtu_base + MTU_LR(0));
	writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
	cr = MTU_CRn_PERIODIC \| MTU_CRn_PRESCALE_1 \| MTU_CRn_32BITS;
	writel(cr, mtu_base + MTU_CR(0));
	writel(cr \| MTU_CRn_ENA, mtu_base + MTU_CR(0));
	}

	void __init nmdk_timer_init(void)		void __init nmdk_timer_init(void)
	{		{
	unsigned long rate;		unsigned long rate;
	int bits;		u32 cr = MTU_CRn_32BITS;;

	rate = CLOCK_TICK_RATE; /* 2.4MHz */		/*
	nmdk_cycle = (rate + HZ/2) / HZ;		* Tick rate is 2.4MHz for Nomadik and 110MHz for ux500:
			* use a divide-by-16 counter if it's more than 16MHz
			*/
			rate = CLOCK_TICK_RATE;
			if (rate > 16 << 20) {
			rate /= 16;
			cr \|= MTU_CRn_PRESCALE_16;
			} else {
			cr \|= MTU_CRn_PRESCALE_1;
			}

	/* Init the timer and register clocksource */		/* Timer 0 is the free running clocksource */
	nmdk_timer_reset();		writel(cr, mtu_base + MTU_CR(0));
			writel(0, mtu_base + MTU_LR(0));
			writel(0, mtu_base + MTU_BGLR(0));
			writel(cr \| MTU_CRn_ENA, mtu_base + MTU_CR(0));

	nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift);		nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift);
	bits = 8*sizeof(nmdk_count);
	nmdk_clksrc.mask = CLOCKSOURCE_MASK(bits);

	if (clocksource_register(&nmdk_clksrc))		if (clocksource_register(&nmdk_clksrc))
	printk(KERN_ERR "timer: failed to initialize clock "		pr_err("timer: failed to initialize clock source %s\n",
	"source %s\n", nmdk_clksrc.name);		nmdk_clksrc.name);

	/* Register irq and clockevents */		/* Timer 1 is used for events, fix according to rate */
	setup_irq(IRQ_MTU0, &nmdk_timer_irq);		writel(cr \| MTU_CRn_ONESHOT, mtu_base + MTU_CR(1)); /* off, currently */
	nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift);		nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift);
			nmdk_clkevt.max_delta_ns =
			clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
			nmdk_clkevt.min_delta_ns =
			clockevent_delta2ns(0x00000002, &nmdk_clkevt);
	nmdk_clkevt.cpumask = cpumask_of(0);		nmdk_clkevt.cpumask = cpumask_of(0);

			/* Register irq and clockevents */
			setup_irq(IRQ_MTU0, &nmdk_timer_irq);
	clockevents_register_device(&nmdk_clkevt);		clockevents_register_device(&nmdk_clkevt);
	}		}