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Commit b0b03546 authored by Tony Truong's avatar Tony Truong
Browse files

ARM: dts: msm: correct REFCLK EN vote for PCIe0 and PCIe1 node on kona 



PCIe0 and PCIe1 should vote for their respective refclk
enable source. Correct the vote in devicetree for PCIe0
and PCIe1 on kona.

Change-Id: I271ecba6c6013ca1337ee9edf2c9898741840766
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent 364475ab

arch/arm64/boot/dts/qcom/kona-pcie.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -67,7 +67,7 @@ 
			<&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>,

			<&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>,

			<&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>,

			<&clock_gcc GCC_PCIE_MDM_CLKREF_EN>,

			<&clock_gcc GCC_PCIE_WIFI_CLKREF_EN>,

			<&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,

			<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,

			<&clock_gcc GCC_PCIE0_PHY_REFGEN_CLK>,
@@ -307,7 +307,7 @@ 
			<&clock_gcc GCC_PCIE_1_CFG_AHB_CLK>,

			<&clock_gcc GCC_PCIE_1_MSTR_AXI_CLK>,

			<&clock_gcc GCC_PCIE_1_SLV_AXI_CLK>,

			<&clock_gcc GCC_PCIE_MDM_CLKREF_EN>,

			<&clock_gcc GCC_PCIE_WIGIG_CLKREF_EN>,

			<&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,

			<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,

			<&clock_gcc GCC_PCIE1_PHY_REFGEN_CLK>,