Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b0205a97 authored by Venkata Narendra Kumar Gutta's avatar Venkata Narendra Kumar Gutta Committed by Rishabh Bhatnagar
Browse files

ARM: dts: msm: Add CPU Subsystem node to kona



Add CPU Subsystem node and the corresponding cache definitions to
kona SoC.

Change-Id: Ia382fd17d14be22b771d1245c42dd28642d2f354
Signed-off-by: default avatarVenkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Signed-off-by: default avatarRishabh Bhatnagar <rishabhb@codeaurora.org>
parent b058dd78
Loading
Loading
Loading
Loading
+335 −3
Original line number Diff line number Diff line
@@ -61,6 +61,20 @@
				      cache-level = <3>;
				};
			};

			L1_I_0: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};

			L1_D_0: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};

			L2_TLB_0: l2-tlb {
				qcom,dump-size = <0x5000>;
			};
		};

		CPU1: cpu@100 {
@@ -80,6 +94,20 @@
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};

			L1_I_100: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};

			L1_D_100: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};

			L2_TLB_100: l2-tlb {
				qcom,dump-size = <0x5000>;
			};
		};

		CPU2: cpu@200 {
@@ -99,6 +127,20 @@
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};

			L1_I_200: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};

			L1_D_200: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};

			L2_TLB_200: l2-tlb {
				qcom,dump-size = <0x5000>;
			};
		};

		CPU3: cpu@300 {
@@ -118,6 +160,20 @@
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};

			L1_I_300: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x8800>;
			};

			L1_D_300: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x9000>;
			};

			L2_TLB_300: l2-tlb {
				qcom,dump-size = <0x5000>;
			};
		};

		CPU4: cpu@400 {
@@ -133,9 +189,32 @@
			dynamic-power-coefficient = <374>;
			L2_4: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-size = <0x40000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			      qcom,dump-size = <0x48000>;
			};

			L1_I_400: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x11000>;
			};

			L1_D_400: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x12000>;
			};

			L1_ITLB_400: l1-itlb {
				qcom,dump-size = <0x300>;
			};

			L1_DTLB_400: l1-dtlb {
				qcom,dump-size = <0x480>;
			};

			L2_TLB_400: l2-tlb {
				qcom,dump-size = <0x7800>;
			};
		};

@@ -152,9 +231,32 @@
			dynamic-power-coefficient = <374>;
			L2_5: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-size = <0x40000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			      qcom,dump-size = <0x48000>;
			};

			L1_I_500: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x11000>;
			};

			L1_D_500: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x12000>;
			};

			L1_ITLB_500: l1-itlb {
				qcom,dump-size = <0x300>;
			};

			L1_DTLB_500: l1-dtlb {
				qcom,dump-size = <0x480>;
			};

			L2_TLB_500: l2-tlb {
				qcom,dump-size = <0x7800>;
			};
		};

@@ -171,9 +273,32 @@
			dynamic-power-coefficient = <374>;
			L2_6: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-size = <0x40000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			      qcom,dump-size = <0x48000>;
			};

			L1_I_600: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x11000>;
			};

			L1_D_600: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x12000>;
			};

			L1_ITLB_600: l1-itlb {
				qcom,dump-size = <0x300>;
			};

			L1_DTLB_600: l1-dtlb {
				qcom,dump-size = <0x480>;
			};

			L2_TLB_600: l2-tlb {
				qcom,dump-size = <0x7800>;
			};
		};

@@ -193,6 +318,29 @@
			      cache-size = <0x80000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			      qcom,dump-size = <0x90000>;
			};

			L1_I_700: l1-icache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x11000>;
			};

			L1_D_700: l1-dcache {
				compatible = "arm,arch-cache";
				qcom,dump-size = <0x12000>;
			};

			L1_ITLB_700: l1-itlb {
				qcom,dump-size = <0x300>;
			};

			L1_DTLB_700: l1-dtlb {
				qcom,dump-size = <0x480>;
			};

			L2_TLB_700: l2-tlb {
				qcom,dump-size = <0x7800>;
			};
		};

@@ -2088,6 +2236,190 @@
		reg = <0xc221000 0x1000>;
		clock-frequency = <32768>;
	};

	cpuss_dump {
		compatible = "qcom,cpuss-dump";

		qcom,l1_i_cache0 {
			qcom,dump-node = <&L1_I_0>;
			qcom,dump-id = <0x60>;
		};

		qcom,l1_i_cache1 {
			qcom,dump-node = <&L1_I_100>;
			qcom,dump-id = <0x61>;
		};

		qcom,l1_i_cache2 {
			qcom,dump-node = <&L1_I_200>;
			qcom,dump-id = <0x62>;
		};

		qcom,l1_i_cache3 {
			qcom,dump-node = <&L1_I_300>;
			qcom,dump-id = <0x63>;
		};

		qcom,l1_i_cache100 {
			qcom,dump-node = <&L1_I_400>;
			qcom,dump-id = <0x64>;
		};

		qcom,l1_i_cache101 {
			qcom,dump-node = <&L1_I_500>;
			qcom,dump-id = <0x65>;
		};

		qcom,l1_i_cache102 {
			qcom,dump-node = <&L1_I_600>;
			qcom,dump-id = <0x66>;
		};

		qcom,l1_i_cache103 {
			qcom,dump-node = <&L1_I_700>;
			qcom,dump-id = <0x67>;
		};

		qcom,l1_d_cache0 {
			qcom,dump-node = <&L1_D_0>;
			qcom,dump-id = <0x80>;
		};

		qcom,l1_d_cache1 {
			qcom,dump-node = <&L1_D_100>;
			qcom,dump-id = <0x81>;
		};

		qcom,l1_d_cache2 {
			qcom,dump-node = <&L1_D_200>;
			qcom,dump-id = <0x82>;
		};

		qcom,l1_d_cache3 {
			qcom,dump-node = <&L1_D_300>;
			qcom,dump-id = <0x83>;
		};

		qcom,l1_d_cache100 {
			qcom,dump-node = <&L1_D_400>;
			qcom,dump-id = <0x84>;
		};

		qcom,l1_d_cache101 {
			qcom,dump-node = <&L1_D_500>;
			qcom,dump-id = <0x85>;
		};

		qcom,l1_d_cache102 {
			qcom,dump-node = <&L1_D_600>;
			qcom,dump-id = <0x86>;
		};

		qcom,l1_d_cache103 {
			qcom,dump-node = <&L1_D_700>;
			qcom,dump-id = <0x87>;
		};

		qcom,l1_i_tlb_dump400 {
			qcom,dump-node = <&L1_ITLB_400>;
			qcom,dump-id = <0x24>;
		};

		qcom,l1_i_tlb_dump500 {
			qcom,dump-node = <&L1_ITLB_500>;
			qcom,dump-id = <0x25>;
		};

		qcom,l1_i_tlb_dump600 {
			qcom,dump-node = <&L1_ITLB_600>;
			qcom,dump-id = <0x26>;
		};

		qcom,l1_i_tlb_dump700 {
			qcom,dump-node = <&L1_ITLB_700>;
			qcom,dump-id = <0x27>;
		};

		qcom,l1_d_tlb_dump400 {
			qcom,dump-node = <&L1_DTLB_400>;
			qcom,dump-id = <0x44>;
		};

		qcom,l1_d_tlb_dump500 {
			qcom,dump-node = <&L1_DTLB_500>;
			qcom,dump-id = <0x45>;
		};

		qcom,l1_d_tlb_dump600 {
			qcom,dump-node = <&L1_DTLB_600>;
			qcom,dump-id = <0x46>;
		};

		qcom,l1_d_tlb_dump700 {
			qcom,dump-node = <&L1_DTLB_700>;
			qcom,dump-id = <0x47>;
		};

		qcom,l2_cache_dump400 {
			qcom,dump-node = <&L2_4>;
			qcom,dump-id = <0xc4>;
		};

		qcom,l2_cache_dump500 {
			qcom,dump-node = <&L2_5>;
			qcom,dump-id = <0xc5>;
		};

		qcom,l2_cache_dump600 {
			qcom,dump-node = <&L2_6>;
			qcom,dump-id = <0xc6>;
		};

		qcom,l2_cache_dump700 {
			qcom,dump-node = <&L2_7>;
			qcom,dump-id = <0xc7>;
		};

		qcom,l2_tlb_dump0 {
			qcom,dump-node = <&L2_TLB_0>;
			qcom,dump-id = <0x120>;
		};

		qcom,l2_tlb_dump100 {
			qcom,dump-node = <&L2_TLB_100>;
			qcom,dump-id = <0x121>;
		};

		qcom,l2_tlb_dump200 {
			qcom,dump-node = <&L2_TLB_200>;
			qcom,dump-id = <0x122>;
		};

		qcom,l2_tlb_dump300 {
			qcom,dump-node = <&L2_TLB_300>;
			qcom,dump-id = <0x123>;
		};

		qcom,l2_tlb_dump400 {
			qcom,dump-node = <&L2_TLB_400>;
			qcom,dump-id = <0x124>;
		};

		qcom,l2_tlb_dump500 {
			qcom,dump-node = <&L2_TLB_500>;
			qcom,dump-id = <0x125>;
		};

		qcom,l2_tlb_dump600 {
			qcom,dump-node = <&L2_TLB_600>;
			qcom,dump-id = <0x126>;
		};

		qcom,l2_tlb_dump700 {
			qcom,dump-node = <&L2_TLB_700>;
			qcom,dump-id = <0x127>;
		};
	};
};

#include "kona-bus.dtsi"