Merge tag 'pm-4.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm

	compatible = "marvell,armada-3700-nb-pm", "syscon";

	reg = <0x14000 0x60>;

}

AVS

---

For AVS an other component is needed:

Required properties:

- compatible     : should contain "marvell,armada-3700-avs", "syscon";

- reg            : the register start and length for the AVS

Example:

avs: avs@11500 {

	compatible = "marvell,armada-3700-avs", "syscon";

	reg = <0x11500 0x40>;

}

Required properties:

- compatible:		 Must be "rockchip,rk3399-dmc".

- devfreq-events:	 Node to get DDR loading, Refer to

			 Documentation/devicetree/bindings/devfreq/

			 Documentation/devicetree/bindings/devfreq/event/

			 rockchip-dfi.txt

- interrupts:		 The interrupt number to the CPU. The interrupt

			 specifier format depends on the interrupt controller.

			 It should be DCF interrupts, when DDR dvfs finish,

			 it will happen.

- clocks:		 Phandles for clock specified in "clock-names" property

- clock-names :		 The name of clock used by the DFI, must be

			 "pclk_ddr_mon";

- center-supply:	 DMC supply node.

- status:		 Marks the node enabled/disabled.

Following properties are ddr timing:

- rockchip,dram_speed_bin :	  Value reference include/dt-bindings/clock/ddr.h,

				  it select ddr3 cl-trp-trcd type, default value

				  "DDR3_DEFAULT".it must selected according to

				  "Speed Bin" in ddr3 datasheet, DO NOT use

				  smaller "Speed Bin" than ddr3 exactly is.

- rockchip,pd_idle :		  Config the PD_IDLE value, defined the power-down

				  idle period, memories are places into power-down

				  mode if bus is idle for PD_IDLE DFI clocks.

- rockchip,sr_idle :		  Configure the SR_IDLE value, defined the

				  selfrefresh idle period, memories are places

				  into self-refresh mode if bus is idle for

				  SR_IDLE*1024 DFI clocks (DFI clocks freq is

				  half of dram's clocks), defaule value is "0".

- rockchip,sr_mc_gate_idle :	  Defined the self-refresh with memory and

				  controller clock gating idle period, memories

				  are places into self-refresh mode and memory

				  controller clock arg gating if bus is idle for

				  sr_mc_gate_idle*1024 DFI clocks.

- rockchip,srpd_lite_idle :	  Defined the self-refresh power down idle

				  period, memories are places into self-refresh

				  power down mode if bus is idle for

				  srpd_lite_idle*1024 DFI clocks. This parameter

				  is for LPDDR4 only.

- rockchip,standby_idle :	  Defined the standby idle period, memories are

				  places into self-refresh than controller, pi,

				  phy and dram clock will gating if bus is idle

				  for standby_idle * DFI clocks.

- rockchip,dram_dll_disb_freq :  It's defined the DDR3 dll bypass frequency in

				  MHz, when ddr freq less than DRAM_DLL_DISB_FREQ,

				  ddr3 dll will bypssed note: if dll was bypassed,

				  the odt also stop working.

- rockchip,phy_dll_disb_freq :	  Defined the PHY dll bypass frequency in

				  MHz (Mega Hz), when ddr freq less than

				  DRAM_DLL_DISB_FREQ, phy dll will bypssed.

				  note: phy dll and phy odt are independent.

- rockchip,ddr3_odt_disb_freq :  When dram type is DDR3, this parameter defined

				  the odt disable frequency in MHz (Mega Hz),

				  when ddr frequency less then ddr3_odt_disb_freq,

				  the odt on dram side and controller side are

Optional properties:

- interrupts:		 The CPU interrupt number. The interrupt specifier

			 format depends on the interrupt controller.

			 It should be a DCF interrupt. When DDR DVFS finishes

			 a DCF interrupt is triggered.

Following properties relate to DDR timing:

- rockchip,dram_speed_bin :	  Value reference include/dt-bindings/clock/rk3399-ddr.h,

				  it selects the DDR3 cl-trp-trcd type. It must be

				  set according to "Speed Bin" in DDR3 datasheet,

				  DO NOT use a smaller "Speed Bin" than specified

				  for the DDR3 being used.

- rockchip,pd_idle :		  Configure the PD_IDLE value. Defines the

				  power-down idle period in which memories are

				  placed into power-down mode if bus is idle

				  for PD_IDLE DFI clock cycles.

- rockchip,sr_idle :		  Configure the SR_IDLE value. Defines the

				  self-refresh idle period in which memories are

				  placed into self-refresh mode if bus is idle

				  for SR_IDLE * 1024 DFI clock cycles (DFI

				  clocks freq is half of DRAM clock), default

				  value is "0".

- rockchip,sr_mc_gate_idle :	  Defines the memory self-refresh and controller

				  clock gating idle period. Memories are placed

				  into self-refresh mode and memory controller

				  clock arg gating started if bus is idle for

				  sr_mc_gate_idle*1024 DFI clock cycles.

- rockchip,srpd_lite_idle :	  Defines the self-refresh power down idle

				  period in which memories are placed into

				  self-refresh power down mode if bus is idle

				  for srpd_lite_idle * 1024 DFI clock cycles.

				  This parameter is for LPDDR4 only.

- rockchip,standby_idle :	  Defines the standby idle period in which

				  memories are placed into self-refresh mode.

				  The controller, pi, PHY and DRAM clock will

				  be gated if bus is idle for standby_idle * DFI

				  clock cycles.

- rockchip,dram_dll_dis_freq :	  Defines the DDR3 DLL bypass frequency in MHz.

				  When DDR frequency is less than DRAM_DLL_DISB_FREQ,

				  DDR3 DLL will be bypassed. Note: if DLL was bypassed,

				  the odt will also stop working.

- rockchip,phy_dll_dis_freq :	  Defines the PHY dll bypass frequency in

				  MHz (Mega Hz). When DDR frequency is less than

				  DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.

				  Note: PHY DLL and PHY ODT are independent.

- rockchip,ddr3_odt_dis_freq :	  When the DRAM type is DDR3, this parameter defines

				  the ODT disable frequency in MHz (Mega Hz).

				  when the DDR frequency is  less then ddr3_odt_dis_freq,

				  the ODT on the DRAM side and controller side are

				  both disabled.

- rockchip,ddr3_drv :		  When dram type is DDR3, this parameter define

				  the dram side driver stength in ohm, default

- rockchip,ddr3_drv :		  When the DRAM type is DDR3, this parameter defines

				  the DRAM side driver strength in ohms. Default

				  value is DDR3_DS_40ohm.

- rockchip,ddr3_odt :		  When dram type is DDR3, this parameter define

				  the dram side ODT stength in ohm, default value

- rockchip,ddr3_odt :		  When the DRAM type is DDR3, this parameter defines

				  the DRAM side ODT strength in ohms. Default value

				  is DDR3_ODT_120ohm.

- rockchip,phy_ddr3_ca_drv :	  When dram type is DDR3, this parameter define

- rockchip,phy_ddr3_ca_drv :	  When the DRAM type is DDR3, this parameter defines

				  the phy side CA line (incluing command line,

				  address line and clock line) driver strength.

				  Default value is PHY_DRV_ODT_40.

- rockchip,phy_ddr3_dq_drv :	  When dram type is DDR3, this parameter define

				  the phy side DQ line(incluing DQS/DQ/DM line)

				  driver strength. default value is PHY_DRV_ODT_40.

- rockchip,phy_ddr3_dq_drv :	  When the DRAM type is DDR3, this parameter defines

				  the PHY side DQ line (including DQS/DQ/DM line)

				  driver strength. Default value is PHY_DRV_ODT_40.

- rockchip,phy_ddr3_odt : 	  When dram type is DDR3, this parameter define the

				  phy side odt strength, default value is

- rockchip,phy_ddr3_odt : 	  When the DRAM type is DDR3, this parameter defines

				  the PHY side ODT strength. Default value is

				  PHY_DRV_ODT_240.

- rockchip,lpddr3_odt_disb_freq : When dram type is LPDDR3, this parameter defined

				  then odt disable frequency in MHz (Mega Hz),

				  when ddr frequency less then ddr3_odt_disb_freq,

				  the odt on dram side and controller side are

- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines

				  then ODT disable frequency in MHz (Mega Hz).

				  When DDR frequency is less then ddr3_odt_dis_freq,

				  the ODT on the DRAM side and controller side are

				  both disabled.

- rockchip,lpddr3_drv :	  When dram type is LPDDR3, this parameter define

				  the dram side driver stength in ohm, default

- rockchip,lpddr3_drv :		  When the DRAM type is LPDDR3, this parameter defines

				  the DRAM side driver strength in ohms. Default

				  value is LP3_DS_34ohm.

- rockchip,lpddr3_odt :	  When dram type is LPDDR3, this parameter define

				  the dram side ODT stength in ohm, default value

- rockchip,lpddr3_odt :		  When the DRAM type is LPDDR3, this parameter defines

				  the DRAM side ODT strength in ohms. Default value

				  is LP3_ODT_240ohm.

- rockchip,phy_lpddr3_ca_drv :	  When dram type is LPDDR3, this parameter define

				  the phy side CA line(incluing command line,

- rockchip,phy_lpddr3_ca_drv :	  When the DRAM type is LPDDR3, this parameter defines

				  the PHY side CA line (including command line,

				  address line and clock line) driver strength.

				  default value is PHY_DRV_ODT_40.

				  Default value is PHY_DRV_ODT_40.

- rockchip,phy_lpddr3_dq_drv :	  When dram type is LPDDR3, this parameter define

				  the phy side DQ line(incluing DQS/DQ/DM line)

				  driver strength. default value is

- rockchip,phy_lpddr3_dq_drv :	  When the DRAM type is LPDDR3, this parameter defines

				  the PHY side DQ line (including DQS/DQ/DM line)

				  driver strength. Default value is

				  PHY_DRV_ODT_40.

- rockchip,phy_lpddr3_odt : 	  When dram type is LPDDR3, this parameter define

				  the phy side odt strength, default value is

				  PHY_DRV_ODT_240.

- rockchip,lpddr4_odt_disb_freq : When dram type is LPDDR4, this parameter

				  defined the odt disable frequency in

				  MHz (Mega Hz), when ddr frequency less then

				  ddr3_odt_disb_freq, the odt on dram side and

- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter

				  defines the ODT disable frequency in

				  MHz (Mega Hz). When the DDR frequency is less then

				  ddr3_odt_dis_freq, the ODT on the DRAM side and

				  controller side are both disabled.

- rockchip,lpddr4_drv :	  When dram type is LPDDR4, this parameter define

				  the dram side driver stength in ohm, default

- rockchip,lpddr4_drv :		  When the DRAM type is LPDDR4, this parameter defines

				  the DRAM side driver strength in ohms. Default

				  value is LP4_PDDS_60ohm.

- rockchip,lpddr4_dq_odt : 	  When dram type is LPDDR4, this parameter define

				  the dram side ODT on dqs/dq line stength in ohm,

				  default value is LP4_DQ_ODT_40ohm.

- rockchip,lpddr4_dq_odt : 	  When the DRAM type is LPDDR4, this parameter defines

				  the DRAM side ODT on DQS/DQ line strength in ohms.

				  Default value is LP4_DQ_ODT_40ohm.

- rockchip,lpddr4_ca_odt :	  When dram type is LPDDR4, this parameter define

				  the dram side ODT on ca line stength in ohm,

				  default value is LP4_CA_ODT_40ohm.

- rockchip,lpddr4_ca_odt :	  When the DRAM type is LPDDR4, this parameter defines

				  the DRAM side ODT on CA line strength in ohms.

				  Default value is LP4_CA_ODT_40ohm.

- rockchip,phy_lpddr4_ca_drv :	  When dram type is LPDDR4, this parameter define

				  the phy side  CA line(incluing command address

				  line) driver strength. default value is

- rockchip,phy_lpddr4_ca_drv :	  When the DRAM type is LPDDR4, this parameter defines

				  the PHY side CA line (including command address

				  line) driver strength. Default value is

				  PHY_DRV_ODT_40.

- rockchip,phy_lpddr4_ck_cs_drv : When dram type is LPDDR4, this parameter define

				  the phy side clock line and cs line driver

				  strength. default value is PHY_DRV_ODT_80.

- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines

				  the PHY side clock line and CS line driver

				  strength. Default value is PHY_DRV_ODT_80.

- rockchip,phy_lpddr4_dq_drv :	  When dram type is LPDDR4, this parameter define

				  the phy side DQ line(incluing DQS/DQ/DM line)

				  driver strength. default value is PHY_DRV_ODT_80.

- rockchip,phy_lpddr4_dq_drv :	  When the DRAM type is LPDDR4, this parameter defines

				  the PHY side DQ line (including DQS/DQ/DM line)

				  driver strength. Default value is PHY_DRV_ODT_80.

- rockchip,phy_lpddr4_odt :	  When dram type is LPDDR4, this parameter define

				  the phy side odt strength, default value is

- rockchip,phy_lpddr4_odt :	  When the DRAM type is LPDDR4, this parameter defines

				  the PHY side ODT strength. Default value is

				  PHY_DRV_ODT_60.

Example:

 - power-domains : A list of PM domain specifiers, as defined by bindings of

		the power controller that is the PM domain provider.

Optional properties:

 - power-domain-names : A list of power domain name strings sorted in the same

		order as the power-domains property. Consumers drivers will use

		power-domain-names to match power domains with power-domains

		specifiers.

Example:

	leaky-device@12350000 {

		compatible = "foo,i-leak-current";

		reg = <0x12350000 0x1000>;

		power-domains = <&power 0>;

		power-domain-names = "io";

	};

	leaky-device@12351000 {

		compatible = "foo,i-leak-current";

		reg = <0x12351000 0x1000>;

		power-domains = <&power 0>, <&power 1> ;

		power-domain-names = "io", "clk";

	};

The first example above defines a typical PM domain consumer device, which is

Two other flags are specifically targeted at use cases where the device

link is added from the consumer's ``->probe`` callback:  ``DL_FLAG_RPM_ACTIVE``

can be specified to runtime resume the supplier upon addition of the

device link.  ``DL_FLAG_AUTOREMOVE`` causes the device link to be automatically

purged when the consumer fails to probe or later unbinds.  This obviates

the need to explicitly delete the link in the ``->remove`` callback or in

the error path of the ``->probe`` callback.

device link.  ``DL_FLAG_AUTOREMOVE_CONSUMER`` causes the device link to be

automatically purged when the consumer fails to probe or later unbinds.

This obviates the need to explicitly delete the link in the ``->remove``

callback or in the error path of the ``->probe`` callback.

Similarly, when the device link is added from supplier's ``->probe`` callback,

``DL_FLAG_AUTOREMOVE_SUPPLIER`` causes the device link to be automatically

purged when the supplier fails to probe or later unbinds.

Limitations

===========

Yes, there are.

First of all, grabbing the 'pm_mutex' lock to mutually exclude a piece of code

First of all, grabbing the 'system_transition_mutex' lock to mutually exclude a piece of code

from system-wide sleep such as suspend/hibernation is not encouraged.

If possible, that piece of code must instead hook onto the suspend/hibernation

notifiers to achieve mutual exclusion. Look at the CPU-Hotplug code

(kernel/cpu.c) for an example.

However, if that is not feasible, and grabbing 'pm_mutex' is deemed necessary,

it is strongly discouraged to directly call mutex_[un]lock(&pm_mutex) since

However, if that is not feasible, and grabbing 'system_transition_mutex' is deemed necessary,

it is strongly discouraged to directly call mutex_[un]lock(&system_transition_mutex) since

that could lead to freezing failures, because if the suspend/hibernate code

successfully acquired the 'pm_mutex' lock, and hence that other entity failed

successfully acquired the 'system_transition_mutex' lock, and hence that other entity failed

to acquire the lock, then that task would get blocked in TASK_UNINTERRUPTIBLE

state. As a consequence, the freezer would not be able to freeze that task,

leading to freezing failure.

However, the [un]lock_system_sleep() APIs are safe to use in this scenario,

since they ask the freezer to skip freezing this task, since it is anyway

"frozen enough" as it is blocked on 'pm_mutex', which will be released

"frozen enough" as it is blocked on 'system_transition_mutex', which will be released

only after the entire suspend/hibernation sequence is complete.

So, to summarize, use [un]lock_system_sleep() instead of directly using

mutex_[un]lock(&pm_mutex). That would prevent freezing failures.

mutex_[un]lock(&system_transition_mutex). That would prevent freezing failures.

V. Miscellaneous

/sys/power/pm_freeze_timeout controls how long it will cost at most to freeze