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Commit afdc71e4 authored by Mark Rustad's avatar Mark Rustad Committed by Jeff Kirsher
Browse files

ixgbe: Fix flow control for Xeon D KR backplane 



Xeon D KR backplane is different from other backplanes,
in that we can't use auto-negotiation to determine the
mode. Instead, use whatever the user configured.

Signed-off-by: default avatarMark Rustad <mark.d.rustad@intel.com>
Tested-by: default avatarPhil Schmitt <phillip.j.schmitt@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent cb2b3edb

drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c

+1 −0
Original line number Diff line number Diff line
@@ -1192,6 +1192,7 @@ static const struct ixgbe_mac_operations mac_ops_82598 = { 
	.clear_vfta		= &ixgbe_clear_vfta_82598,

	.set_vfta		= &ixgbe_set_vfta_82598,

	.fc_enable		= &ixgbe_fc_enable_82598,

	.setup_fc		= ixgbe_setup_fc_generic,

	.set_fw_drv_ver         = NULL,

	.acquire_swfw_sync      = &ixgbe_acquire_swfw_sync,

	.release_swfw_sync      = &ixgbe_release_swfw_sync,

drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c

+1 −0
Original line number Diff line number Diff line
@@ -2220,6 +2220,7 @@ static const struct ixgbe_mac_operations mac_ops_82599 = { 
	.clear_vfta             = &ixgbe_clear_vfta_generic,

	.set_vfta               = &ixgbe_set_vfta_generic,

	.fc_enable              = &ixgbe_fc_enable_generic,

	.setup_fc		= ixgbe_setup_fc_generic,

	.set_fw_drv_ver         = &ixgbe_set_fw_drv_ver_generic,

	.init_uta_tables        = &ixgbe_init_uta_tables_generic,

	.setup_sfp              = &ixgbe_setup_sfp_modules_82599,

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

+4 −4
Original line number Diff line number Diff line 
/*******************************************************************************



  Intel 10 Gigabit PCI Express Linux driver

  Copyright(c) 1999 - 2015 Intel Corporation.

  Copyright(c) 1999 - 2016 Intel Corporation.



  This program is free software; you can redistribute it and/or modify it

  under the terms and conditions of the GNU General Public License,
@@ -111,12 +111,12 @@ bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 
}



/**

 *  ixgbe_setup_fc - Set up flow control

 *  ixgbe_setup_fc_generic - Set up flow control

 *  @hw: pointer to hardware structure

 *

 *  Called at init time to set up flow control.

 **/

static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)

s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw)

{

	s32 ret_val = 0;

	u32 reg = 0, reg_bp = 0;
@@ -296,7 +296,7 @@ s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 
	IXGBE_WRITE_FLUSH(hw);



	/* Setup flow control */

	ret_val = ixgbe_setup_fc(hw);

	ret_val = hw->mac.ops.setup_fc(hw);

	if (ret_val)

		return ret_val;

drivers/net/ethernet/intel/ixgbe/ixgbe_common.h

+2 −1
Original line number Diff line number Diff line 
/*******************************************************************************



  Intel 10 Gigabit PCI Express Linux driver

  Copyright(c) 1999 - 2014 Intel Corporation.

  Copyright(c) 1999 - 2016 Intel Corporation.



  This program is free software; you can redistribute it and/or modify it

  under the terms and conditions of the GNU General Public License,
@@ -81,6 +81,7 @@ s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw); 
s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw);

s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);

s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw);

s32 ixgbe_setup_fc_generic(struct ixgbe_hw *);

bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);

void ixgbe_fc_autoneg(struct ixgbe_hw *hw);

drivers/net/ethernet/intel/ixgbe/ixgbe_type.h

+5 −0
Original line number Diff line number Diff line
@@ -3308,6 +3308,7 @@ struct ixgbe_mac_operations { 


	/* Flow Control */

	s32 (*fc_enable)(struct ixgbe_hw *);

	s32 (*setup_fc)(struct ixgbe_hw *);



	/* Manageability interface */

	s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
@@ -3525,6 +3526,7 @@ struct ixgbe_info { 


#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P)	((P) ? 0x8010 : 0x4010)

#define IXGBE_KRM_LINK_CTRL_1(P)	((P) ? 0x820C : 0x420C)

#define IXGBE_KRM_AN_CNTL_1(P)		((P) ? 0x822C : 0x422C)

#define IXGBE_KRM_DSP_TXFFE_STATE_4(P)	((P) ? 0x8634 : 0x4634)

#define IXGBE_KRM_DSP_TXFFE_STATE_5(P)	((P) ? 0x8638 : 0x4638)

#define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P)	((P) ? 0x8B00 : 0x4B00)
@@ -3547,6 +3549,9 @@ struct ixgbe_info { 
#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE		(1 << 29)

#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART		(1 << 31)



#define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE			(1 << 28)

#define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE			(1 << 29)



#define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN			(1 << 6)

#define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN		(1 << 15)

#define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN		(1 << 16)