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Commit afb0e7e9 authored by Pratham Pratap's avatar Pratham Pratap
Browse files

ARM: dts: msm: Update QMP PHY parameters 

This change updates QMP PHY parameters as per
HPG.

Change-Id: Ia2ba942e74b5e0f1fa7bc82ff5e970231293c0da
parent 08da6d24

qcom/lito-usb.dtsi

+21 −21
Original line number Diff line number Diff line
@@ -170,8 +170,8 @@ 
			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0

			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x05 0

			USB3_DP_QSERDES_TXA_LANE_MODE_1 0xD5 0

			USB3_DP_QSERDES_TXA_LANE_MODE_2 0x2A 0

			USB3_DP_QSERDES_TXA_LANE_MODE_1 0x55 0

			USB3_DP_QSERDES_TXA_LANE_MODE_2 0x02 0

			USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F 0

			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0

			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x20 0
@@ -186,7 +186,7 @@ 
			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x05 0

			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x05 0

			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0

			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0E 0

			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x08 0

			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0

			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0

			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
@@ -200,26 +200,26 @@ 
			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x3F 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x7F 0

			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x94 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xDC 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x5C 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x0B 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xB3 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x5B 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x1B 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xD2 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x13 0

			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xA9 0

			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0

			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0

			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x00 0

			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0

			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0

			USB3_DP_QSERDES_RXA_GM_CAL 0x1F 0

			USB3_DP_QSERDES_RXA_GM_CAL 0x00 0

			USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0

			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x05 0

			USB3_DP_QSERDES_TXB_LANE_MODE_1 0xD5 0

			USB3_DP_QSERDES_TXB_LANE_MODE_2 0x2A 0

			USB3_DP_QSERDES_TXB_LANE_MODE_1 0x55 0

			USB3_DP_QSERDES_TXB_LANE_MODE_2 0x02 0

			USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F 0

			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0

			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x20 0

			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x02 0

			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0

			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0

			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
@@ -231,7 +231,7 @@ 
			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x05 0

			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x05 0

			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0

			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0E 0

			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x08 0

			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0

			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0

			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
@@ -245,16 +245,16 @@ 
			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x3F 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x7F 0

			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x94 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xDC 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x5C 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x0B 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xB3 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x5B 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x1B 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xD2 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x13 0

			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xA9 0

			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0

			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0

			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x00 0

			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0

			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0

			USB3_DP_QSERDES_RXB_GM_CAL 0x1F 0

			USB3_DP_QSERDES_RXB_GM_CAL 0x00 0

			USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0 0

			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0