Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit af96f07f authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "arm64: compat: Add separate CP15 trapping hook"

parents 0fa6b01b 406aee66

arch/arm64/include/asm/esr.h

+52 −0
Original line number Diff line number Diff line
@@ -249,6 +249,58 @@ 


#define ESR_ELx_FP_EXC_TFV	(UL(1) << 23)



/*

 * ISS field definitions for CP15 accesses

 */

#define ESR_ELx_CP15_32_ISS_DIR_MASK	0x1

#define ESR_ELx_CP15_32_ISS_DIR_READ	0x1

#define ESR_ELx_CP15_32_ISS_DIR_WRITE	0x0



#define ESR_ELx_CP15_32_ISS_RT_SHIFT	5

#define ESR_ELx_CP15_32_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)

#define ESR_ELx_CP15_32_ISS_CRM_SHIFT	1

#define ESR_ELx_CP15_32_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)

#define ESR_ELx_CP15_32_ISS_CRN_SHIFT	10

#define ESR_ELx_CP15_32_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)

#define ESR_ELx_CP15_32_ISS_OP1_SHIFT	14

#define ESR_ELx_CP15_32_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)

#define ESR_ELx_CP15_32_ISS_OP2_SHIFT	17

#define ESR_ELx_CP15_32_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)



#define ESR_ELx_CP15_32_ISS_SYS_MASK	(ESR_ELx_CP15_32_ISS_OP1_MASK | \

					 ESR_ELx_CP15_32_ISS_OP2_MASK | \

					 ESR_ELx_CP15_32_ISS_CRN_MASK | \

					 ESR_ELx_CP15_32_ISS_CRM_MASK | \

					 ESR_ELx_CP15_32_ISS_DIR_MASK)

#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \

					(((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \

					 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \

					 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \

					 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))



#define ESR_ELx_CP15_64_ISS_DIR_MASK	0x1

#define ESR_ELx_CP15_64_ISS_DIR_READ	0x1

#define ESR_ELx_CP15_64_ISS_DIR_WRITE	0x0



#define ESR_ELx_CP15_64_ISS_RT_SHIFT	5

#define ESR_ELx_CP15_64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)



#define ESR_ELx_CP15_64_ISS_RT2_SHIFT	10

#define ESR_ELx_CP15_64_ISS_RT2_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)



#define ESR_ELx_CP15_64_ISS_OP1_SHIFT	16

#define ESR_ELx_CP15_64_ISS_OP1_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)

#define ESR_ELx_CP15_64_ISS_CRM_SHIFT	1

#define ESR_ELx_CP15_64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)



#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \

					(((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \

					 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))



#define ESR_ELx_CP15_64_ISS_SYS_MASK	(ESR_ELx_CP15_64_ISS_OP1_MASK |	\

					 ESR_ELx_CP15_64_ISS_CRM_MASK | \

					 ESR_ELx_CP15_64_ISS_DIR_MASK)



#ifndef __ASSEMBLY__

#include <asm/types.h>

arch/arm64/kernel/entry.S

+13 −2
Original line number Diff line number Diff line
@@ -697,9 +697,9 @@ el0_sync_compat: 
	cmp	x24, #ESR_ELx_EC_UNKNOWN	// unknown exception in EL0

	b.eq	el0_undef

	cmp	x24, #ESR_ELx_EC_CP15_32	// CP15 MRC/MCR trap

	b.eq	el0_undef

	b.eq	el0_cp15

	cmp	x24, #ESR_ELx_EC_CP15_64	// CP15 MRRC/MCRR trap

	b.eq	el0_undef

	b.eq	el0_cp15

	cmp	x24, #ESR_ELx_EC_CP14_MR	// CP14 MRC/MCR trap

	b.eq	el0_undef

	cmp	x24, #ESR_ELx_EC_CP14_LS	// CP14 LDC/STC trap
@@ -722,6 +722,17 @@ el0_irq_compat: 
el0_error_compat:

	kernel_entry 0, 32

	b	el0_error_naked



el0_cp15:

	/*

	 * Trapped CP15 (MRC, MCR, MRRC, MCRR) instructions

	 */

	enable_daif

	ct_user_exit

	mov	x0, x25

	mov	x1, sp

	bl	do_cp15instr

	b	ret_to_user

#endif



el0_da:

arch/arm64/kernel/traps.c

+13 −0
Original line number Diff line number Diff line
@@ -534,6 +534,19 @@ static struct sys64_hook sys64_hooks[] = { 
	{},

};





#ifdef CONFIG_COMPAT

asmlinkage void __exception do_cp15instr(unsigned int esr, struct pt_regs *regs)

{

	/*

	 * New cp15 instructions may previously have been undefined at

	 * EL0. Fall back to our usual undefined instruction handler

	 * so that we handle these consistently.

	 */

	do_undefinstr(regs);

}

#endif



asmlinkage void __exception do_sysinstr(unsigned int esr, struct pt_regs *regs)

{

	struct sys64_hook *hook;