Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit af7d5e77 authored by Siddartha Mohanadoss's avatar Siddartha Mohanadoss
Browse files

dt-bindings: Add bindings for ADC5 driver 



Add devicetree bindings for ADC5 peripheral driver.

Change-Id: I4079ea002a810a4cfc53dcb159a56757af1d3f24
Signed-off-by: default avatarSiddartha Mohanadoss <smohanad@codeaurora.org>
parent 404a89ab

Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5.txt

0 → 100644
+166 −0
Original line number Diff line number Diff line 
Qualcomm Technologies Inc. SPMI PMIC5 voltage and current ADC



SPMI PMIC5 voltage ADC (ADC) provides interface to clients to read

voltage. The ADC is a 15-bit sigma-delta ADC.



ADC node:



- compatible:

    Usage: required

    Value type: <string>

    Definition: Should contain "qcom,spmi-adc5" for PMIC5 ADC driver.

		Should contain "qcom,spmi-adc-rev2" for PMIC refresh ADC driver.



- reg:

    Usage: required for VADC base address

    Value type: <prop-encoded-array>

    Definition: VADC base address and length in the SPMI PMIC register map.

                ADC_CAL base address and length in SPMI PMIC register map.

                ADC_CAL base is optional and is dependent on USB_IN_V channel

                read sequence for the PMIC.



- reg-names

    Usage: required

    Value type: <string>

    Definition: Names associated with base addresses. should be

                "adc5-usr-base", "adc5-cal-base".



- #address-cells:

    Usage: required

    Value type: <u32>

    Definition: Must be one. Child node 'reg' property should define ADC

            channel number.



- #size-cells:

    Usage: required

    Value type: <u32>

    Definition: Must be zero.



- #io-channel-cells:

    Usage: required

    Value type: <u32>

    Definition: Must be one. For details about IIO bindings see:

            Documentation/devicetree/bindings/iio/iio-bindings.txt



- interrupts:

    Usage: optional

    Value type: <prop-encoded-array>

    Definition: End of conversion interrupt.



- qcom,pmic-revid:

    Usage: optional

    Value type:<u32>

    Definition: phandle pointing to the revision peripheral node. Use it to query the

                PMIC type and revision.



Channel node properties:



- reg:

    Usage: required

    Value type: <u32>

    Definition: ADC channel number.

            See include/dt-bindings/iio/qcom,spmi-vadc.h



- label:

    Usage: required

    Value type: <empty>

    Definition: ADC datasheet channel name.

            For thermistor inputs connected to generic AMUX or GPIO inputs

            these can vary across platform for the same pins. Hence select

            the datasheet name for this channel.



- qcom,pre-scaling:

    Usage: required

    Value type: <u32 array>

    Definition: Used for scaling the channel input signal before the signal is

            fed to VADC. The configuration for this node is to know the

            pre-determined ratio and use it for post scaling. Select one from

            the following options.

            <1 1>, <1 3>, <1 4>, <1 6>, <1 20>, <1 8>, <10 81>, <1 10>

            If property is not found default value depending on chip will be used.



- qcom,decimation:

    Usage: optional

    Value type: <u32>

    Definition: This parameter is used to decrease ADC sampling rate.

            Quicker measurements can be made by reducing decimation ratio.

            For PMIC5 ADC, combined two step decimation values are 250, 420 and 840.

            If property is not found, default value of 840 will be used.

	    For PMIC refresh ADC, supported decimation values are 256, 512, 1024.

	    If property is not found, default value of 1024 will be used.



- qcom,ratiometric:

    Usage: optional

    Value type: <empty>

    Definition: Channel calibration type. If this property is specified

            VADC will use the VDD reference (1.875V) and GND for channel

            calibration. If property is not found, channel will be

            calibrated with 0V and 1.25V reference channels, also

            known as absolute calibration.



- qcom,hw-settle-time:

    Usage: optional

    Value type: <u32>

    Definition: Time between AMUX getting configured and the ADC starting

            conversion.

	    For PMIC5, delay = 15us for value 0,

			100us * (value) for values 0 < value < 11, and

			2ms * (value - 10) otherwise.

            Valid values are: 15, 100, 200, 300, 400, 500, 600, 700, 800,

            900 us and 1, 2, 4, 6, 8, 10 ms

            If property is not found, channel will use 15us.

	    For PMIC rev2, delay = 100us * (value) for values 0 < value < 11, and

			2ms * (value - 10) otherwise.

            Valid values are: 0, 100, 200, 300, 400, 500, 600, 700, 800,

            900 us and 1, 2, 4, 6, 8, 10 ms

            If property is not found, channel will use 0 us.



- qcom,avg-samples:

    Usage: optional

    Value type: <u32>

    Definition: Number of samples to be used for measurement.

            Averaging provides the option to obtain a single measurement

            from the ADC that is an average of multiple samples. The value

            selected is 2^(value).

            Valid values are: 1, 2, 4, 8, 16

            If property is not found, 1 sample will be used.



- qcom,lut-index:

    Usage: optional

    Value type: <u32>

    Definition: Lookup table index (only for bat_therm channels).

            A bat_therm channel (for 30k, 100k or 400k pull-up resistance)

            requires a voltage-temperature look-up table which depends on the target.

            The LUT to be used for a channel is selected from a table of LUTs

            for that particular channel.

            If property is not found, a default LUT is used for that channel,

            corresponding to index 0.



Example:



        /* VADC node */

        pmic_vadc: vadc@3100 {

                compatible = "qcom,spmi-adc5";

                reg = <0x3100 0x100>;

                interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;

                #address-cells = <1>;

                #size-cells = <0>;

                #io-channel-cells = <1>;

                io-channel-ranges;



                /* Channel node */

                vph_pwr {

                        reg = <ADC_VPH_PWR>;

                        label = "vph_pwr";

                        qcom,decimation = <840>;

                        qcom,hw-settle-time = <0>;

                        qcom,avg-samples = <1>;

                        qcom,pre-scaling = <1 3>;

                };

        };



        /* IIO client node */

        usb {

                io-channels = <&pmic_vadc ADC_VPH_PWR>;

                io-channel-names = "vadc";

        };

include/dt-bindings/iio/qcom,spmi-vadc.h

+116 −10
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 * Copyright (c) 2012-2014,2018-2019 The Linux Foundation. All rights reserved.

 */





#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H

#define _DT_BINDINGS_QCOM_SPMI_VADC_H
@@ -116,4 +109,117 @@ 
#define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID	0xf9

#define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM	0xfc



/* ADC channels for SPMI VADC5*/



#define ADC_REF_GND				0x00

#define ADC_1P25VREF				0x01

#define ADC_VREF_VADC				0x02

#define ADC_VREF_VADC_DIV_3			0x82

#define ADC_VPH_PWR				0x83

#define ADC_VBAT_SNS				0x84

#define ADC_VCOIN				0x85

#define ADC_DIE_TEMP				0x06

#define ADC_USB_IN_I				0x07

#define ADC_USB_IN_V_16				0x08

#define ADC_CHG_TEMP				0x09

#define ADC_BAT_THERM				0x0a

#define ADC_BAT_ID				0x0b

#define ADC_XO_THERM				0x0c

#define ADC_AMUX_THM1				0x0d

#define ADC_AMUX_THM2				0x0e

#define ADC_AMUX_THM3				0x0f

#define ADC_AMUX_THM4				0x10

#define ADC_AMUX_THM5				0x11

#define ADC_GPIO1				0x12

#define ADC_GPIO2				0x13

#define ADC_GPIO3				0x14

#define ADC_GPIO4				0x15

#define ADC_GPIO5				0x16

#define ADC_GPIO6				0x17

#define ADC_GPIO7				0x18

#define ADC_SBUx				0x99

#define ADC_MID_CHG_DIV6			0x1e

#define ADC_OFF					0xff



/* 30k pull-up1 */

#define ADC_BAT_THERM_PU1			0x2a

#define ADC_BAT_ID_PU1				0x2b

#define ADC_XO_THERM_PU1			0x2c

#define ADC_AMUX_THM1_PU1			0x2d

#define ADC_AMUX_THM2_PU1			0x2e

#define ADC_AMUX_THM3_PU1			0x2f

#define ADC_AMUX_THM4_PU1			0x30

#define ADC_AMUX_THM5_PU1			0x31

#define ADC_GPIO1_PU1				0x32

#define ADC_GPIO2_PU1				0x33

#define ADC_GPIO3_PU1				0x34

#define ADC_GPIO4_PU1				0x35

#define ADC_GPIO5_PU1				0x36

#define ADC_GPIO6_PU1				0x37

#define ADC_GPIO7_PU1				0x38

#define ADC_SBUx_PU1				0x39



/* 100k pull-up2 */

#define ADC_BAT_THERM_PU2			0x4a

#define ADC_BAT_ID_PU2				0x4b

#define ADC_XO_THERM_PU2			0x4c

#define ADC_AMUX_THM1_PU2			0x4d

#define ADC_AMUX_THM2_PU2			0x4e

#define ADC_AMUX_THM3_PU2			0x4f

#define ADC_AMUX_THM4_PU2			0x50

#define ADC_AMUX_THM5_PU2			0x51

#define ADC_GPIO1_PU2				0x52

#define ADC_GPIO2_PU2				0x53

#define ADC_GPIO3_PU2				0x54

#define ADC_GPIO4_PU2				0x55

#define ADC_GPIO5_PU2				0x56

#define ADC_GPIO6_PU2				0x57

#define ADC_GPIO7_PU2				0x58

#define ADC_SBUx_PU2				0x59



/* 400k pull-up3 */

#define ADC_BAT_THERM_PU3			0x6a

#define ADC_BAT_ID_PU3				0x6b

#define ADC_XO_THERM_PU3			0x6c

#define ADC_AMUX_THM1_PU3			0x6d

#define ADC_AMUX_THM2_PU3			0x6e

#define ADC_AMUX_THM3_PU3			0x6f

#define ADC_AMUX_THM4_PU3			0x70

#define ADC_AMUX_THM5_PU3			0x71

#define ADC_GPIO1_PU3				0x72

#define ADC_GPIO2_PU3				0x73

#define ADC_GPIO3_PU3				0x74

#define ADC_GPIO4_PU3				0x75

#define ADC_GPIO5_PU3				0x76

#define ADC_GPIO6_PU3				0x77

#define ADC_GPIO7_PU3				0x78

#define ADC_SBUx_PU3				0x79



/* 1/3 Divider */

#define ADC_GPIO1_DIV3				0x92

#define ADC_GPIO2_DIV3				0x93

#define ADC_GPIO3_DIV3				0x94

#define ADC_GPIO4_DIV3				0x95

#define ADC_GPIO5_DIV3				0x96

#define ADC_GPIO6_DIV3				0x97

#define ADC_GPIO7_DIV3				0x98

#define ADC_SBUx_DIV3				0x99



/* Current and combined current/voltage channels */

#define ADC_INT_EXT_ISENSE			0xa1

#define ADC_PARALLEL_ISENSE			0xa5

#define ADC_CUR_REPLICA_VDS			0xa7

#define ADC_CUR_SENS_BATFET_VDS_OFFSET		0xa9

#define ADC_CUR_SENS_REPLICA_VDS_OFFSET		0xab

#define ADC_EXT_SENS_OFFSET			0xad



#define ADC_INT_EXT_ISENSE_VBAT_VDATA		0xb0

#define ADC_INT_EXT_ISENSE_VBAT_IDATA		0xb1

#define ADC_EXT_ISENSE_VBAT_VDATA		0xb2

#define ADC_EXT_ISENSE_VBAT_IDATA		0xb3

#define ADC_PARALLEL_ISENSE_VBAT_VDATA		0xb4

#define ADC_PARALLEL_ISENSE_VBAT_IDATA		0xb5



#define ADC_MAX_CHANNEL				0xc0



#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */