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Unverified Commit aef13fd8 authored by Jernej Skrabec's avatar Jernej Skrabec Committed by Maxime Ripard
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drm/sun4i: DW HDMI PHY: Add support for second PLL 



Some DW HDMI PHYs, like those found in A64 and R40 SoCs, can select
between two clock parents.

Add code which reads second PLL from DT.

Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180625120304.7543-19-jernej.skrabec@siol.net
parent 09f380e3

drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h

+2 −0
Original line number Diff line number Diff line
@@ -147,6 +147,7 @@ struct sun8i_hdmi_phy; 


struct sun8i_hdmi_phy_variant {

	bool has_phy_clk;

	bool has_second_pll;

	void (*phy_init)(struct sun8i_hdmi_phy *phy);

	void (*phy_disable)(struct dw_hdmi *hdmi,

			    struct sun8i_hdmi_phy *phy);
@@ -160,6 +161,7 @@ struct sun8i_hdmi_phy { 
	struct clk			*clk_mod;

	struct clk			*clk_phy;

	struct clk			*clk_pll0;

	struct clk			*clk_pll1;

	unsigned int			rcal;

	struct regmap			*regs;

	struct reset_control		*rst_phy;

drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c

+15 −5
Original line number Diff line number Diff line
@@ -482,10 +482,19 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) 
			goto err_put_clk_mod;

		}



		if (phy->variant->has_second_pll) {

			phy->clk_pll1 = of_clk_get_by_name(node, "pll-1");

			if (IS_ERR(phy->clk_pll1)) {

				dev_err(dev, "Could not get pll-1 clock\n");

				ret = PTR_ERR(phy->clk_pll1);

				goto err_put_clk_pll0;

			}

		}



		ret = sun8i_phy_clk_create(phy, dev);

		if (ret) {

			dev_err(dev, "Couldn't create the PHY clock\n");

			goto err_put_clk_pll0;

			goto err_put_clk_pll1;

		}



		clk_prepare_enable(phy->clk_phy);
@@ -528,8 +537,9 @@ int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) 
	reset_control_put(phy->rst_phy);

err_disable_clk_phy:

	clk_disable_unprepare(phy->clk_phy);

err_put_clk_pll1:

	clk_put(phy->clk_pll1);

err_put_clk_pll0:

	if (phy->variant->has_phy_clk)

	clk_put(phy->clk_pll0);

err_put_clk_mod:

	clk_put(phy->clk_mod);
@@ -551,8 +561,8 @@ void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi) 


	reset_control_put(phy->rst_phy);



	if (phy->variant->has_phy_clk)

	clk_put(phy->clk_pll0);

	clk_put(phy->clk_pll1);

	clk_put(phy->clk_mod);

	clk_put(phy->clk_bus);

}