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Commit aeb99c85 authored by Neil Armstrong's avatar Neil Armstrong Committed by Linus Walleij
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dt-bindings: Add Oxford Semiconductor OXNAS pinctrl and gpio bindings



Add pinctrl and gpio DT bindings for Oxford Semiconductor OXNAS SoC Family.
This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins.

Signed-off-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 611dac1e
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* Oxford Semiconductor OXNAS SoC GPIO Controller

Please refer to gpio.txt for generic information regarding GPIO bindings.

Required properties:
 - compatible: "oxsemi,ox810se-gpio"
 - reg: Base address and length for the device.
 - interrupts: The port interrupt shared by all pins.
 - gpio-controller: Marks the port as GPIO controller.
 - #gpio-cells: Two. The first cell is the pin number and
   the second cell is used to specify the gpio polarity as defined in
   defined in <dt-bindings/gpio/gpio.h>:
      0 = GPIO_ACTIVE_HIGH
      1 = GPIO_ACTIVE_LOW
 - interrupt-controller: Marks the device node as an interrupt controller.
 - #interrupt-cells: Two. The first cell is the GPIO number and second cell
   is used to specify the trigger type as defined in
   <dt-bindings/interrupt-controller/irq.h>:
      IRQ_TYPE_EDGE_RISING
      IRQ_TYPE_EDGE_FALLING
      IRQ_TYPE_EDGE_BOTH
 - gpio-ranges: Interaction with the PINCTRL subsystem, it also specifies the
   gpio base and count, should be in the format of numeric-gpio-range as
   specified in the gpio.txt file.

Example:

gpio0: gpio@0 {
	compatible = "oxsemi,ox810se-gpio";
	reg = <0x000000 0x100000>;
	interrupts = <21>;
	#gpio-cells = <2>;
	gpio-controller;
	interrupt-controller;
	#interrupt-cells = <2>;
	gpio-ranges = <&pinctrl 0 0 32>;
};

keys {
	...

	button-esc {
		label = "ESC";
		linux,code = <1>;
		gpios = <&gpio0 12 0>;
	};
};
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* Oxford Semiconductor OXNAS SoC Family Pin Controller

Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
../interrupt-controller/interrupts.txt for generic information regarding
pin controller, GPIO, and interrupt bindings.

OXNAS 'pin configuration node' is a node of a group of pins which can be
used for a specific device or function. This node represents configurations of
pins, optional function, and optional mux related configuration.

Required properties for pin controller node:
 - compatible: "oxsemi,ox810se-pinctrl"
 - oxsemi,sys-ctrl: a phandle to the system controller syscon node

Required properties for pin configuration sub-nodes:
 - pins: List of pins to which the configuration applies.

Optional properties for pin configuration sub-nodes:
----------------------------------------------------
 - function: Mux function for the specified pins.
 - bias-pull-up: Enable weak pull-up.

Example:

pinctrl: pinctrl {
	compatible = "oxsemi,ox810se-pinctrl";

	/* Regmap for sys registers */
	oxsemi,sys-ctrl = <&sys>;

	pinctrl_uart2: pinctrl_uart2 {
		uart2a {
			pins = "gpio31";
			function = "fct3";
		};
		uart2b {
			pins = "gpio32";
			function = "fct3";
		};
	};
};

uart2: serial@900000 {
	compatible = "ns16550a";
	reg = <0x900000 0x100000>;
	clocks = <&sysclk>;
	interrupts = <29>;
	reg-shift = <0>;
	fifo-size = <16>;
	reg-io-width = <1>;
	current-speed = <115200>;
	no-loopback-test;
	status = "disabled";
	resets = <&reset 22>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
};