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Commit ae706beb authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'juno-fixes-4.12' of... 

Merge tag 'juno-fixes-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt64

Pull "ARMv8 Juno DT fixes for v4.12" from Sudeep Holla:

1. Couple of fixes to remove device tree warnings introduced with
   recently added checks in DTC

2. Add information about L1 and L2 caches to Juno device trees as
   CCSIDR-based cacheinfo probing is now removed

* tag 'juno-fixes-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  arm64: dts: juno: add information about L1 and L2 caches
  arm64: dts: juno: fix few unit address format warnings
  arm64: dts: juno: fix PCI bus dtc warnings
parents d0815dfd f9936c4a

arch/arm64/boot/dts/arm/juno-base.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -428,7 +428,7 @@ 
		};

	};



	pcie_ctlr: pcie-controller@40000000 {

	pcie_ctlr: pcie@40000000 {

		compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";

		device_type = "pci";

		reg = <0 0x40000000 0 0x10000000>;	/* ECAM config space */
@@ -699,7 +699,7 @@ 
		      <0x00000008 0x80000000 0x1 0x80000000>;

	};



	smb@08000000 {

	smb@8000000 {

		compatible = "simple-bus";

		#address-cells = <2>;

		#size-cells = <1>;

arch/arm64/boot/dts/arm/juno-motherboard.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -137,7 +137,7 @@ 
				#size-cells = <1>;

				ranges = <0 3 0 0x200000>;



				v2m_sysctl: sysctl@020000 {

				v2m_sysctl: sysctl@20000 {

					compatible = "arm,sp810", "arm,primecell";

					reg = <0x020000 0x1000>;

					clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
@@ -148,7 +148,7 @@ 
					assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;

				};



				apbregs@010000 {

				apbregs@10000 {

					compatible = "syscon", "simple-mfd";

					reg = <0x010000 0x1000>;
@@ -216,7 +216,7 @@ 
					};

				};



				mmci@050000 {

				mmci@50000 {

					compatible = "arm,pl180", "arm,primecell";

					reg = <0x050000 0x1000>;

					interrupts = <5>;
@@ -228,7 +228,7 @@ 
					clock-names = "mclk", "apb_pclk";

				};



				kmi@060000 {

				kmi@60000 {

					compatible = "arm,pl050", "arm,primecell";

					reg = <0x060000 0x1000>;

					interrupts = <8>;
@@ -236,7 +236,7 @@ 
					clock-names = "KMIREFCLK", "apb_pclk";

				};



				kmi@070000 {

				kmi@70000 {

					compatible = "arm,pl050", "arm,primecell";

					reg = <0x070000 0x1000>;

					interrupts = <8>;
@@ -244,7 +244,7 @@ 
					clock-names = "KMIREFCLK", "apb_pclk";

				};



				wdt@0f0000 {

				wdt@f0000 {

					compatible = "arm,sp805", "arm,primecell";

					reg = <0x0f0000 0x10000>;

					interrupts = <7>;

arch/arm64/boot/dts/arm/juno-r1.dts

+42 −0
Original line number Diff line number Diff line
@@ -89,6 +89,12 @@ 
			reg = <0x0 0x0>;

			device_type = "cpu";

			enable-method = "psci";

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&A57_L2>;

			clocks = <&scpi_dvfs 0>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -100,6 +106,12 @@ 
			reg = <0x0 0x1>;

			device_type = "cpu";

			enable-method = "psci";

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&A57_L2>;

			clocks = <&scpi_dvfs 0>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -111,6 +123,12 @@ 
			reg = <0x0 0x100>;

			device_type = "cpu";

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -122,6 +140,12 @@ 
			reg = <0x0 0x101>;

			device_type = "cpu";

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -133,6 +157,12 @@ 
			reg = <0x0 0x102>;

			device_type = "cpu";

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -144,6 +174,12 @@ 
			reg = <0x0 0x103>;

			device_type = "cpu";

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -152,10 +188,16 @@ 


		A57_L2: l2-cache0 {

			compatible = "cache";

			cache-size = <0x200000>;

			cache-line-size = <64>;

			cache-sets = <2048>;

		};



		A53_L2: l2-cache1 {

			compatible = "cache";

			cache-size = <0x100000>;

			cache-line-size = <64>;

			cache-sets = <1024>;

		};

	};

arch/arm64/boot/dts/arm/juno-r2.dts

+42 −0
Original line number Diff line number Diff line
@@ -89,6 +89,12 @@ 
			reg = <0x0 0x0>;

			device_type = "cpu";

			enable-method = "psci";

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&A72_L2>;

			clocks = <&scpi_dvfs 0>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -100,6 +106,12 @@ 
			reg = <0x0 0x1>;

			device_type = "cpu";

			enable-method = "psci";

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&A72_L2>;

			clocks = <&scpi_dvfs 0>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -111,6 +123,12 @@ 
			reg = <0x0 0x100>;

			device_type = "cpu";

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -122,6 +140,12 @@ 
			reg = <0x0 0x101>;

			device_type = "cpu";

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -133,6 +157,12 @@ 
			reg = <0x0 0x102>;

			device_type = "cpu";

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -144,6 +174,12 @@ 
			reg = <0x0 0x103>;

			device_type = "cpu";

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -152,10 +188,16 @@ 


		A72_L2: l2-cache0 {

			compatible = "cache";

			cache-size = <0x200000>;

			cache-line-size = <64>;

			cache-sets = <2048>;

		};



		A53_L2: l2-cache1 {

			compatible = "cache";

			cache-size = <0x100000>;

			cache-line-size = <64>;

			cache-sets = <1024>;

		};

	};

arch/arm64/boot/dts/arm/juno.dts

+42 −0
Original line number Diff line number Diff line
@@ -88,6 +88,12 @@ 
			reg = <0x0 0x0>;

			device_type = "cpu";

			enable-method = "psci";

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&A57_L2>;

			clocks = <&scpi_dvfs 0>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -99,6 +105,12 @@ 
			reg = <0x0 0x1>;

			device_type = "cpu";

			enable-method = "psci";

			i-cache-size = <0xc000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <256>;

			next-level-cache = <&A57_L2>;

			clocks = <&scpi_dvfs 0>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -110,6 +122,12 @@ 
			reg = <0x0 0x100>;

			device_type = "cpu";

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -121,6 +139,12 @@ 
			reg = <0x0 0x101>;

			device_type = "cpu";

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -132,6 +156,12 @@ 
			reg = <0x0 0x102>;

			device_type = "cpu";

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -143,6 +173,12 @@ 
			reg = <0x0 0x103>;

			device_type = "cpu";

			enable-method = "psci";

			i-cache-size = <0x8000>;

			i-cache-line-size = <64>;

			i-cache-sets = <256>;

			d-cache-size = <0x8000>;

			d-cache-line-size = <64>;

			d-cache-sets = <128>;

			next-level-cache = <&A53_L2>;

			clocks = <&scpi_dvfs 1>;

			cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
@@ -151,10 +187,16 @@ 


		A57_L2: l2-cache0 {

			compatible = "cache";

			cache-size = <0x200000>;

			cache-line-size = <64>;

			cache-sets = <2048>;

		};



		A53_L2: l2-cache1 {

			compatible = "cache";

			cache-size = <0x100000>;

			cache-line-size = <64>;

			cache-sets = <1024>;

		};

	};