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Commit ae5702d2 authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Make IS_GENx macros work on a mask 



If instead of numerical comparison me make these test a
bitmask, we enable the compiler to optimize all instances
of IS_GENx || IS_GENy.

v2: Make bit zero of gen mask mean gen 1.

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent dc97997a

drivers/gpu/drm/i915/i915_dma.c

+3 −0
Original line number Diff line number Diff line
@@ -1073,6 +1073,9 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv, 
	memcpy(device_info, info, sizeof(dev_priv->info));

	device_info->device_id = dev->pdev->device;



	BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);

	device_info->gen_mask = BIT(device_info->gen - 1);



	spin_lock_init(&dev_priv->irq_lock);

	spin_lock_init(&dev_priv->gpu_error.lock);

	mutex_init(&dev_priv->backlight_lock);

drivers/gpu/drm/i915/i915_drv.h

+9 −8
Original line number Diff line number Diff line
@@ -760,6 +760,7 @@ struct intel_device_info { 
	u8 num_pipes:3;

	u8 num_sprites[I915_MAX_PIPES];

	u8 gen;

	u16 gen_mask;

	u8 ring_mask; /* Rings supported by the HW */

	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);

	/* Register offsets for the various display pipes and transcoders */
@@ -2620,14 +2621,14 @@ struct drm_i915_cmd_table { 
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular

 * chips, etc.).

 */

#define IS_GEN2(dev)	(INTEL_INFO(dev)->gen == 2)

#define IS_GEN3(dev)	(INTEL_INFO(dev)->gen == 3)

#define IS_GEN4(dev)	(INTEL_INFO(dev)->gen == 4)

#define IS_GEN5(dev)	(INTEL_INFO(dev)->gen == 5)

#define IS_GEN6(dev)	(INTEL_INFO(dev)->gen == 6)

#define IS_GEN7(dev)	(INTEL_INFO(dev)->gen == 7)

#define IS_GEN8(dev)	(INTEL_INFO(dev)->gen == 8)

#define IS_GEN9(dev)	(INTEL_INFO(dev)->gen == 9)

#define IS_GEN2(dev)	(INTEL_INFO(dev)->gen_mask & BIT(1))

#define IS_GEN3(dev)	(INTEL_INFO(dev)->gen_mask & BIT(2))

#define IS_GEN4(dev)	(INTEL_INFO(dev)->gen_mask & BIT(3))

#define IS_GEN5(dev)	(INTEL_INFO(dev)->gen_mask & BIT(4))

#define IS_GEN6(dev)	(INTEL_INFO(dev)->gen_mask & BIT(5))

#define IS_GEN7(dev)	(INTEL_INFO(dev)->gen_mask & BIT(6))

#define IS_GEN8(dev)	(INTEL_INFO(dev)->gen_mask & BIT(7))

#define IS_GEN9(dev)	(INTEL_INFO(dev)->gen_mask & BIT(8))



#define RENDER_RING		(1<<RCS)

#define BSD_RING		(1<<VCS)

drivers/gpu/drm/i915/intel_uncore.c

+2 −2
Original line number Diff line number Diff line
@@ -1391,7 +1391,7 @@ void intel_uncore_fini(struct drm_i915_private *dev_priv) 
	intel_uncore_forcewake_reset(dev_priv, false);

}



#define GEN_RANGE(l, h) GENMASK(h, l)

#define GEN_RANGE(l, h) GENMASK((h) - 1, (l) - 1)



static const struct register_whitelist {

	i915_reg_t offset_ldw, offset_udw;
@@ -1416,7 +1416,7 @@ int i915_reg_read_ioctl(struct drm_device *dev, 


	for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {

		if (i915_mmio_reg_offset(entry->offset_ldw) == (reg->offset & -entry->size) &&

		    (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))

		    (INTEL_INFO(dev)->gen_mask & entry->gen_bitmask))

			break;

	}