Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ae247d60 authored by Uwe Kleine-König's avatar Uwe Kleine-König Committed by Greg Kroah-Hartman
Browse files

gpio: mvebu: only fail on missing clk if pwm is actually to be used



[ Upstream commit c8da642d41a6811c21177c9994aa7dc35be67d46 ]

The gpio IP on Armada 370 at offset 0x18180 has neither a clk nor pwm
registers. So there is no need for a clk as the pwm isn't used anyhow.
So only check for the clk in the presence of the pwm registers. This fixes
a failure to probe the gpio driver for the above mentioned gpio device.

Fixes: 757642f9 ("gpio: mvebu: Add limited PWM support")
Signed-off-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: default avatarGregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 332fc667
Loading
Loading
Loading
Loading
+3 −3
Original line number Diff line number Diff line
@@ -773,9 +773,6 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
				     "marvell,armada-370-gpio"))
		return 0;

	if (IS_ERR(mvchip->clk))
		return PTR_ERR(mvchip->clk);

	/*
	 * There are only two sets of PWM configuration registers for
	 * all the GPIO lines on those SoCs which this driver reserves
@@ -786,6 +783,9 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
	if (!res)
		return 0;

	if (IS_ERR(mvchip->clk))
		return PTR_ERR(mvchip->clk);

	/*
	 * Use set A for lines of GPIO chip with id 0, B for GPIO chip
	 * with id 1. Don't allow further GPIO chips to be used for PWM.