[POWERPC] Import spu disassembly code into xmon

/* Disassemble SPU instructions

   Copyright 2006 Free Software Foundation, Inc.

   This file is part of GDB, GAS, and the GNU binutils.

   This program is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 2 of the License, or

   (at your option) any later version.

   This program is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License along

   with this program; if not, write to the Free Software Foundation, Inc.,

   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */

#include <linux/string.h>

#include "nonstdio.h"

#include "ansidecl.h"

#include "spu.h"

extern void print_address (unsigned long memaddr);

/* This file provides a disassembler function which uses

   the disassembler interface defined in dis-asm.h.   */

extern const struct spu_opcode spu_opcodes[];

extern const int spu_num_opcodes;

#define SPU_DISASM_TBL_SIZE (1 << 11)

static const struct spu_opcode *spu_disassemble_table[SPU_DISASM_TBL_SIZE];

static void

init_spu_disassemble (void)

{

  int i;

  /* If two instructions have the same opcode then we prefer the first

   * one.  In most cases it is just an alternate mnemonic. */

  for (i = 0; i < spu_num_opcodes; i++)

    {

      int o = spu_opcodes[i].opcode;

      if (o >= SPU_DISASM_TBL_SIZE)

	continue; /* abort (); */

      if (spu_disassemble_table[o] == 0)

	spu_disassemble_table[o] = &spu_opcodes[i];

    }

}

/* Determine the instruction from the 10 least significant bits. */

static const struct spu_opcode *

get_index_for_opcode (unsigned int insn)

{

  const struct spu_opcode *index;

  unsigned int opcode = insn >> (32-11);

  /* Init the table.  This assumes that element 0/opcode 0 (currently

   * NOP) is always used */

  if (spu_disassemble_table[0] == 0)

    init_spu_disassemble ();

  if ((index = spu_disassemble_table[opcode & 0x780]) != 0

      && index->insn_type == RRR)

    return index;

  if ((index = spu_disassemble_table[opcode & 0x7f0]) != 0

      && (index->insn_type == RI18 || index->insn_type == LBT))

    return index;

  if ((index = spu_disassemble_table[opcode & 0x7f8]) != 0

      && index->insn_type == RI10)

    return index;

  if ((index = spu_disassemble_table[opcode & 0x7fc]) != 0

      && (index->insn_type == RI16))

    return index;

  if ((index = spu_disassemble_table[opcode & 0x7fe]) != 0

      && (index->insn_type == RI8))

    return index;

  if ((index = spu_disassemble_table[opcode & 0x7ff]) != 0)

    return index;

  return 0;

}

/* Print a Spu instruction.  */

int

print_insn_spu (unsigned long insn, unsigned long memaddr)

{

  int value;

  int hex_value;

  const struct spu_opcode *index;

  enum spu_insns tag;

  index = get_index_for_opcode (insn);

  if (index == 0)

    {

      printf(".long 0x%x", insn);

    }

  else

    {

      int i;

      int paren = 0;

      tag = (enum spu_insns)(index - spu_opcodes);

      printf("%s", index->mnemonic);

      if (tag == M_BI || tag == M_BISL || tag == M_IRET || tag == M_BISLED

	  || tag == M_BIHNZ || tag == M_BIHZ || tag == M_BINZ || tag == M_BIZ

          || tag == M_SYNC || tag == M_HBR)

	{

	  int fb = (insn >> (32-18)) & 0x7f;

	  if (fb & 0x40)

	    printf(tag == M_SYNC ? "c" : "p");

	  if (fb & 0x20)

	    printf("d");

	  if (fb & 0x10)

	    printf("e");

	}

      if (index->arg[0] != 0)

	printf("\t");

      hex_value = 0;

      for (i = 1;  i <= index->arg[0]; i++)

	{

	  int arg = index->arg[i];

	  if (arg != A_P && !paren && i > 1)

	    printf(",");

	  switch (arg)

	    {

	    case A_T:

	      printf("$%d",

				     DECODE_INSN_RT (insn));

	      break;

	    case A_A:

	      printf("$%d",

				     DECODE_INSN_RA (insn));

	      break;

	    case A_B:

	      printf("$%d",

				     DECODE_INSN_RB (insn));

	      break;

	    case A_C:

	      printf("$%d",

				     DECODE_INSN_RC (insn));

	      break;

	    case A_S:

	      printf("$sp%d",

				     DECODE_INSN_RA (insn));

	      break;

	    case A_H:

	      printf("$ch%d",

				     DECODE_INSN_RA (insn));

	      break;

	    case A_P:

	      paren++;

	      printf("(");

	      break;

	    case A_U7A:

	      printf("%d",

				     173 - DECODE_INSN_U8 (insn));

	      break;

	    case A_U7B:

	      printf("%d",

				     155 - DECODE_INSN_U8 (insn));

	      break;

	    case A_S3:

	    case A_S6:

	    case A_S7:

	    case A_S7N:

	    case A_U3:

	    case A_U5:

	    case A_U6:

	    case A_U7:

	      hex_value = DECODE_INSN_I7 (insn);

	      printf("%d", hex_value);

	      break;

	    case A_S11:

	      print_address(memaddr + DECODE_INSN_I9a (insn) * 4);

	      break;

	    case A_S11I:

	      print_address(memaddr + DECODE_INSN_I9b (insn) * 4);

	      break;

	    case A_S10:

	    case A_S10B:

	      hex_value = DECODE_INSN_I10 (insn);

	      printf("%d", hex_value);

	      break;

	    case A_S14:

	      hex_value = DECODE_INSN_I10 (insn) * 16;

	      printf("%d", hex_value);

	      break;

	    case A_S16:

	      hex_value = DECODE_INSN_I16 (insn);

	      printf("%d", hex_value);

	      break;

	    case A_X16:

	      hex_value = DECODE_INSN_U16 (insn);

	      printf("%u", hex_value);

	      break;

	    case A_R18:

	      value = DECODE_INSN_I16 (insn) * 4;

	      if (value == 0)

		printf("%d", value);

	      else

		{

		  hex_value = memaddr + value;

		  print_address(hex_value & 0x3ffff);

		}

	      break;

	    case A_S18:

	      value = DECODE_INSN_U16 (insn) * 4;

	      if (value == 0)

		printf("%d", value);

	      else

		print_address(value);

	      break;

	    case A_U18:

	      value = DECODE_INSN_U18 (insn);

	      if (value == 0 || 1)

		{

		  hex_value = value;

		  printf("%u", value);

		}

	      else

		print_address(value);

	      break;

	    case A_U14:

	      hex_value = DECODE_INSN_U14 (insn);

	      printf("%u", hex_value);

	      break;

	    }

	  if (arg != A_P && paren)

	    {

	      printf(")");

	      paren--;

	    }

	}

      if (hex_value > 16)

	printf("\t# %x", hex_value);

    }

  return 4;

}

/* SPU opcode list

   Copyright 2006 Free Software Foundation, Inc.

   This file is part of GDB, GAS, and the GNU binutils.

   This program is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 2 of the License, or

   (at your option) any later version.

   This program is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License along

   with this program; if not, write to the Free Software Foundation, Inc.,

   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */

#include "spu.h"

/* This file holds the Spu opcode table */

/*

   Example contents of spu-insn.h

      id_tag	mode	mode	type	opcode	mnemonic	asmtype	    dependency		FPU	L/S?	branch?	instruction   

                QUAD	WORD                                               (0,RC,RB,RA,RT)    latency  			              		

   APUOP(M_LQD,	1,	0,	RI9,	0x1f8,	"lqd",		ASM_RI9IDX,	00012,		FXU,	1,	0)	Load Quadword d-form 

 */

const struct spu_opcode spu_opcodes[] = {

#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \

	{ MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },

#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \

	{ MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },

#include "spu-insns.h"

#undef APUOP

#undef APUOPFB

};

const int spu_num_opcodes =

  sizeof (spu_opcodes) / sizeof (spu_opcodes[0]);

/* SPU ELF support for BFD.

   Copyright 2006 Free Software Foundation, Inc.

   This file is part of GDB, GAS, and the GNU binutils.

   This program is free software; you can redistribute it and/or modify

   it under the terms of the GNU General Public License as published by

   the Free Software Foundation; either version 2 of the License, or

   (at your option) any later version.

   This program is distributed in the hope that it will be useful,

   but WITHOUT ANY WARRANTY; without even the implied warranty of

   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License

   along with this program; if not, write to the Free Software Foundation,

   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */

/* These two enums are from rel_apu/common/spu_asm_format.h */

/* definition of instruction format */

typedef enum {

  RRR,

  RI18,

  RI16,

  RI10,

  RI8,

  RI7,

  RR,

  LBT,

  LBTI,

  IDATA,

  UNKNOWN_IFORMAT

} spu_iformat;

/* These values describe assembly instruction arguments.  They indicate

 * how to encode, range checking and which relocation to use. */

typedef enum {

  A_T,  /* register at pos 0 */

  A_A,  /* register at pos 7 */

  A_B,  /* register at pos 14 */

  A_C,  /* register at pos 21 */

  A_S,  /* special purpose register at pos 7 */

  A_H,  /* channel register at pos 7 */

  A_P,  /* parenthesis, this has to separate regs from immediates */

  A_S3,

  A_S6,

  A_S7N,

  A_S7,

  A_U7A,

  A_U7B,

  A_S10B,

  A_S10,

  A_S11,

  A_S11I,

  A_S14,

  A_S16,

  A_S18,

  A_R18,

  A_U3,

  A_U5,

  A_U6,

  A_U7,

  A_U14,

  A_X16,

  A_U18,

  A_MAX

} spu_aformat;

enum spu_insns {

#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \

	TAG,

#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \

	TAG,

#include "spu-insns.h"

#undef APUOP

#undef APUOPFB

        M_SPU_MAX

};

struct spu_opcode

{

   spu_iformat insn_type;

   unsigned int opcode;

   char *mnemonic;

   int arg[5];

};

#define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size))

#define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1))

#define DECODE_INSN_RT(insn) (insn & 0x7f)

#define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f)

#define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f)

#define DECODE_INSN_RC(insn) ((insn >> 21) & 0x7f)

#define DECODE_INSN_I10(insn) SIGNED_EXTRACT(insn,10,14)

#define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT(insn,10,14)

/* For branching, immediate loads, hbr and  lqa/stqa. */

#define DECODE_INSN_I16(insn) SIGNED_EXTRACT(insn,16,7)

#define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT(insn,16,7)

/* for stop */

#define DECODE_INSN_U14(insn) UNSIGNED_EXTRACT(insn,14,0)

/* For ila */

#define DECODE_INSN_I18(insn) SIGNED_EXTRACT(insn,18,7)

#define DECODE_INSN_U18(insn) UNSIGNED_EXTRACT(insn,18,7)

/* For rotate and shift and generate control mask */

#define DECODE_INSN_I7(insn) SIGNED_EXTRACT(insn,7,14)

#define DECODE_INSN_U7(insn) UNSIGNED_EXTRACT(insn,7,14)

/* For float <-> int conversion */

#define DECODE_INSN_I8(insn)  SIGNED_EXTRACT(insn,8,14)

#define DECODE_INSN_U8(insn) UNSIGNED_EXTRACT(insn,8,14)

/* For hbr  */

#define DECODE_INSN_I9a(insn) ((SIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))

#define DECODE_INSN_I9b(insn) ((SIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))

#define DECODE_INSN_U9a(insn) ((UNSIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0))

#define DECODE_INSN_U9b(insn) ((UNSIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0))