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Commit ad8046a5 authored by Steve Longerbeam's avatar Steve Longerbeam Committed by Shawn Guo
Browse files

ARM: dts: imx6-sabreauto: add the ADV7180 video decoder 



Enables the ADV7180 decoder sensor. The ADV7180 connects to the
parallel-bus mux input on ipu1_csi0_mux.

The ADV7180 power pin is via max7310_b port expander.

Changes from Tim Harvey:
- Use IRQ_TYPE_LEVEL_LOW instead of 0x8 for interrupt type for clarity.
- For 8-bit parallel IPU1-CSI0 bus connection only data[12-19] are used.

Signed-off-by: default avatarSteve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: default avatarTim Harvey <tharvey@gateworks.com>
Reviewed-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent ba410540

arch/arm/boot/dts/imx6qdl-sabreauto.dtsi

+45 −0
Original line number Diff line number Diff line
@@ -124,6 +124,21 @@ 
			#size-cells = <0>;

			reg = <1>;



			adv7180: camera@21 {

				compatible = "adi,adv7180";

				reg = <0x21>;

				powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;

				interrupt-parent = <&gpio1>;

				interrupts = <27 IRQ_TYPE_LEVEL_LOW>;



				port {

					adv7180_to_ipu1_csi0_mux: endpoint {

						remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;

						bus-width = <8>;

					};

				};

			};



			max7310_a: gpio@30 {

				compatible = "maxim,max7310";

				reg = <0x30>;
@@ -151,6 +166,20 @@ 
	};

};



&ipu1_csi0_from_ipu1_csi0_mux {

	bus-width = <8>;

};



&ipu1_csi0_mux_from_parallel_sensor {

	remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;

	bus-width = <8>;

};



&ipu1_csi0 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_ipu1_csi0>;

};



&clks {

	assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,

			  <&clks IMX6QDL_PLL4_BYPASS>,
@@ -444,6 +473,22 @@ 
			>;

		};



		pinctrl_ipu1_csi0: ipu1csi0grp {

			fsl,pins = <

				MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12  0x1b0b0

				MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13  0x1b0b0

				MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14  0x1b0b0

				MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15  0x1b0b0

				MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16  0x1b0b0

				MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17  0x1b0b0

				MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18  0x1b0b0

				MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19  0x1b0b0

				MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0

				MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC    0x1b0b0

				MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC   0x1b0b0

			>;

		};



		pinctrl_max7310: max7310grp {

			fsl,pins = <

				MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0