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Commit ad58d4d4 authored by James Hogan's avatar James Hogan
Browse files

KVM: MIPS/T&E: Expose read-only CP0_IntCtl register 



Expose the CP0_IntCtl register through the KVM register access API,
which is a required register since MIPS32r2. It is currently read-only
since the VS field isn't implemented due to lack of Config3.VInt or
Config3.VEIC.

It is implemented in trap_emul.c so that a VZ implementation can allow
writes.

Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
parent 013044cc

Documentation/virtual/kvm/api.txt

+1 −0
Original line number Diff line number Diff line
@@ -2073,6 +2073,7 @@ registers, find a list below: 
  MIPS  | KVM_REG_MIPS_CP0_ENTRYHI      | 64

  MIPS  | KVM_REG_MIPS_CP0_COMPARE      | 32

  MIPS  | KVM_REG_MIPS_CP0_STATUS       | 32

  MIPS  | KVM_REG_MIPS_CP0_INTCTL       | 32

  MIPS  | KVM_REG_MIPS_CP0_CAUSE        | 32

  MIPS  | KVM_REG_MIPS_CP0_EPC          | 64

  MIPS  | KVM_REG_MIPS_CP0_PRID         | 32

arch/mips/include/asm/kvm_host.h

+1 −0
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ 
#define KVM_REG_MIPS_CP0_ENTRYHI	MIPS_CP0_64(10, 0)

#define KVM_REG_MIPS_CP0_COMPARE	MIPS_CP0_32(11, 0)

#define KVM_REG_MIPS_CP0_STATUS		MIPS_CP0_32(12, 0)

#define KVM_REG_MIPS_CP0_INTCTL		MIPS_CP0_32(12, 1)

#define KVM_REG_MIPS_CP0_CAUSE		MIPS_CP0_32(13, 0)

#define KVM_REG_MIPS_CP0_EPC		MIPS_CP0_64(14, 0)

#define KVM_REG_MIPS_CP0_PRID		MIPS_CP0_32(15, 0)

arch/mips/kvm/trap_emul.c

+7 −0
Original line number Diff line number Diff line
@@ -658,6 +658,7 @@ static u64 kvm_trap_emul_get_one_regs[] = { 
	KVM_REG_MIPS_CP0_ENTRYHI,

	KVM_REG_MIPS_CP0_COMPARE,

	KVM_REG_MIPS_CP0_STATUS,

	KVM_REG_MIPS_CP0_INTCTL,

	KVM_REG_MIPS_CP0_CAUSE,

	KVM_REG_MIPS_CP0_EPC,

	KVM_REG_MIPS_CP0_PRID,
@@ -741,6 +742,9 @@ static int kvm_trap_emul_get_one_reg(struct kvm_vcpu *vcpu, 
	case KVM_REG_MIPS_CP0_STATUS:

		*v = (long)kvm_read_c0_guest_status(cop0);

		break;

	case KVM_REG_MIPS_CP0_INTCTL:

		*v = (long)kvm_read_c0_guest_intctl(cop0);

		break;

	case KVM_REG_MIPS_CP0_CAUSE:

		*v = (long)kvm_read_c0_guest_cause(cop0);

		break;
@@ -855,6 +859,9 @@ static int kvm_trap_emul_set_one_reg(struct kvm_vcpu *vcpu, 
	case KVM_REG_MIPS_CP0_STATUS:

		kvm_write_c0_guest_status(cop0, v);

		break;

	case KVM_REG_MIPS_CP0_INTCTL:

		/* No VInt, so no VS, read-only for now */

		break;

	case KVM_REG_MIPS_CP0_EPC:

		kvm_write_c0_guest_epc(cop0, v);

		break;