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Commit ad574189 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "cnss2: Add support for dumping bulk registers for debugging"

parents 508ddee6 2600852a

drivers/net/wireless/cnss2/pci.c

+333 −69
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#include "bus.h"

#include "debug.h"

#include "pci.h"

#include "reg.h"



#define PCI_LINK_UP			1

#define PCI_LINK_DOWN			0
@@ -57,79 +58,10 @@ static DEFINE_SPINLOCK(pci_reg_window_lock); 


#define MHI_TIMEOUT_OVERWRITE_MS	(plat_priv->ctrl_params.mhi_timeout)



#define QCA6390_PCIE_REMAP_BAR_CTRL_OFFSET	0x310C



#define QCA6390_CE_SRC_RING_REG_BASE		0xA00000

#define QCA6390_CE_DST_RING_REG_BASE		0xA01000

#define QCA6390_CE_COMMON_REG_BASE		0xA18000



#define QCA6390_CE_SRC_RING_BASE_LSB_OFFSET	0x0

#define QCA6390_CE_SRC_RING_BASE_MSB_OFFSET	0x4

#define QCA6390_CE_SRC_RING_ID_OFFSET		0x8

#define QCA6390_CE_SRC_RING_MISC_OFFSET		0x10

#define QCA6390_CE_SRC_CTRL_OFFSET		0x58

#define QCA6390_CE_SRC_R0_CE_CH_SRC_IS_OFFSET	0x5C

#define QCA6390_CE_SRC_RING_HP_OFFSET		0x400

#define QCA6390_CE_SRC_RING_TP_OFFSET		0x404



#define QCA6390_CE_DEST_RING_BASE_LSB_OFFSET	0x0

#define QCA6390_CE_DEST_RING_BASE_MSB_OFFSET	0x4

#define QCA6390_CE_DEST_RING_ID_OFFSET		0x8

#define QCA6390_CE_DEST_RING_MISC_OFFSET	0x10

#define QCA6390_CE_DEST_CTRL_OFFSET		0xB0

#define QCA6390_CE_CH_DST_IS_OFFSET		0xB4

#define QCA6390_CE_CH_DEST_CTRL2_OFFSET		0xB8

#define QCA6390_CE_DEST_RING_HP_OFFSET		0x400

#define QCA6390_CE_DEST_RING_TP_OFFSET		0x404



#define QCA6390_CE_STATUS_RING_BASE_LSB_OFFSET	0x58

#define QCA6390_CE_STATUS_RING_BASE_MSB_OFFSET	0x5C

#define QCA6390_CE_STATUS_RING_ID_OFFSET	0x60

#define QCA6390_CE_STATUS_RING_MISC_OFFSET	0x68

#define QCA6390_CE_STATUS_RING_HP_OFFSET	0x408

#define QCA6390_CE_STATUS_RING_TP_OFFSET	0x40C



#define QCA6390_CE_COMMON_GXI_ERR_INTS		0x14

#define QCA6390_CE_COMMON_GXI_ERR_STATS		0x18

#define QCA6390_CE_COMMON_GXI_WDOG_STATUS	0x2C

#define QCA6390_CE_COMMON_TARGET_IE_0		0x48

#define QCA6390_CE_COMMON_TARGET_IE_1		0x4C



#define QCA6390_CE_REG_INTERVAL			0x2000



#define SHADOW_REG_COUNT			36

#define QCA6390_PCIE_SHADOW_REG_VALUE_0		0x8FC

#define QCA6390_PCIE_SHADOW_REG_VALUE_34	0x984

#define QCA6390_PCIE_SHADOW_REG_VALUE_35	0x988

#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL3	0x1F80118

#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL4	0x1F8011C

#define QCA6390_WLAON_GLOBAL_COUNTER_CTRL5	0x1F80120



#define SHADOW_REG_INTER_COUNT			43

#define QCA6390_PCIE_SHADOW_REG_INTER_0		0x1E05000

#define QCA6390_PCIE_SHADOW_REG_HUNG		0x1E050A8



#define QDSS_APB_DEC_CSR_BASE			0x1C01000



#define QDSS_APB_DEC_CSR_ETRIRQCTRL_OFFSET	0x6C

#define QDSS_APB_DEC_CSR_PRESERVEETF_OFFSET	0x70

#define QDSS_APB_DEC_CSR_PRESERVEETR0_OFFSET	0x74

#define QDSS_APB_DEC_CSR_PRESERVEETR1_OFFSET	0x78



#define MAX_UNWINDOWED_ADDRESS			0x80000

#define WINDOW_ENABLE_BIT			0x40000000

#define WINDOW_SHIFT				19

#define WINDOW_VALUE_MASK			0x3F

#define WINDOW_START				MAX_UNWINDOWED_ADDRESS

#define WINDOW_RANGE_MASK			0x7FFFF



#define FORCE_WAKE_DELAY_MIN_US			4000

#define FORCE_WAKE_DELAY_MAX_US			6000

#define FORCE_WAKE_DELAY_TIMEOUT_US		60000



#define QCA6390_TIME_SYNC_ENABLE		0x80000000

#define QCA6390_TIME_SYNC_CLEAR			0x0



static struct cnss_pci_reg ce_src[] = {

	{ "SRC_RING_BASE_LSB", QCA6390_CE_SRC_RING_BASE_LSB_OFFSET },

	{ "SRC_RING_BASE_MSB", QCA6390_CE_SRC_RING_BASE_MSB_OFFSET },
@@ -178,6 +110,240 @@ static struct cnss_pci_reg qdss_csr[] = { 
	{ NULL },

};



static struct cnss_misc_reg wcss_reg_access_seq[] = {

	{0, QCA6390_GCC_DEBUG_CLK_CTL, 0},

	{1, QCA6390_GCC_DEBUG_CLK_CTL, 0x802},

	{0, QCA6390_GCC_DEBUG_CLK_CTL, 0},

	{0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_PLL_MODE, 0},

	{1, QCA6390_GCC_DEBUG_CLK_CTL, 0x805},

	{0, QCA6390_GCC_DEBUG_CLK_CTL, 0},

	{0, QCA6390_WCSS_WFSS_PMM_WFSS_PMM_R0_PMM_CTRL, 0},

	{0, QCA6390_WCSS_PMM_TOP_PMU_CX_CSR, 0},

	{0, QCA6390_WCSS_PMM_TOP_AON_INT_RAW_STAT, 0},

	{0, QCA6390_WCSS_PMM_TOP_AON_INT_EN, 0},

	{0, QCA6390_WCSS_PMM_TOP_PMU_TESTBUS_STS, 0},

	{1, QCA6390_WCSS_PMM_TOP_PMU_TESTBUS_CTL, 0xD},

	{0, QCA6390_WCSS_PMM_TOP_TESTBUS_STS, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_CFG, 0},

	{1, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_CFG, 0},

	{1, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL, 0x8},

	{0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_STS, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_CTL, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_SLP_SEQ_ENTRY_0, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_SPM_SLP_SEQ_ENTRY_9, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS0, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS1, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS2, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS3, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS4, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS5, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_STATUS6, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE0, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE1, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE2, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE3, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE4, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE5, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_ENABLE6, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING0, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING1, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING2, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING3, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING4, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING5, 0},

	{0, QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_INT_PENDING6, 0},

	{1, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL, 0x30040},

	{0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL, 0},

	{0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0},

	{0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0},

	{0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0},

	{1, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL, 0x30105},

	{0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL, 0},

	{0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0},

	{0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0},

	{0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0},

	{0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0},

	{0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0},

	{0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0},

	{0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_VALUE, 0},

	{0, QCA6390_WCSS_Q6SS_PUBCSR_QDSP6SS_TEST_BUS_CTL, 0},

	{0, QCA6390_WCSS_CC_WCSS_UMAC_NOC_CBCR, 0},

	{0, QCA6390_WCSS_CC_WCSS_UMAC_AHB_CBCR, 0},

	{0, QCA6390_WCSS_CC_WCSS_UMAC_GDSCR, 0},

	{0, QCA6390_WCSS_CC_WCSS_WLAN1_GDSCR, 0},

	{0, QCA6390_WCSS_CC_WCSS_WLAN2_GDSCR, 0},

	{0, QCA6390_WCSS_PMM_TOP_PMM_INT_CLR, 0},

	{0, QCA6390_WCSS_PMM_TOP_AON_INT_STICKY_EN, 0},

};



static struct cnss_misc_reg pcie_reg_access_seq[] = {

	{0, QCA6390_PCIE_PCIE_WCSS_STATUS_FOR_DEBUG_LOW_PCIE_LOCAL_REG, 0},

	{0, QCA6390_PCIE_SOC_PCIE_WRAP_INTR_MASK_SOC_PCIE_REG, 0},

	{1, QCA6390_PCIE_SOC_PCIE_WRAP_INTR_MASK_SOC_PCIE_REG, 0x18},

	{0, QCA6390_PCIE_SOC_PCIE_WRAP_INTR_MASK_SOC_PCIE_REG, 0},

	{0, QCA6390_PCIE_SOC_PCIE_WRAP_INTR_MASK_SOC_PCIE_REG, 0},

	{0, QCA6390_PCIE_SOC_PCIE_WRAP_INTR_STATUS_SOC_PCIE_REG, 0},

	{0, QCA6390_PCIE_SOC_COMMIT_REPLAY_SOC_PCIE_REG, 0},

	{0, QCA6390_TLMM_GPIO_IN_OUT57, 0},

	{0, QCA6390_TLMM_GPIO_INTR_CFG57, 0},

	{0, QCA6390_TLMM_GPIO_INTR_STATUS57, 0},

	{0, QCA6390_TLMM_GPIO_IN_OUT59, 0},

	{0, QCA6390_TLMM_GPIO_INTR_CFG59, 0},

	{0, QCA6390_TLMM_GPIO_INTR_STATUS59, 0},

	{0, QCA6390_PCIE_PCIE_PARF_LTSSM, 0},

	{0, QCA6390_PCIE_PCIE_PARF_PM_STTS, 0},

	{0, QCA6390_PCIE_PCIE_PARF_PM_STTS_1, 0},

	{0, QCA6390_PCIE_PCIE_PARF_INT_STATUS, 0},

	{0, QCA6390_PCIE_PCIE_INT_ALL_STATUS, 0},

	{0, QCA6390_PCIE_PCIE_INT_ALL_MASK, 0},

	{0, QCA6390_PCIE_PCIE_PARF_BDF_TO_SID_CFG, 0},

	{0, QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_NO_MHI_ACCESS_HANDLER_RD_4, 0},

	{0, QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_NO_MHI_ACCESS_HANDLER_RD_3, 0},

	{0, QCA6390_PCIE_PCIE_PARF_MHI_CLOCK_RESET_CTRL, 0},

	{0, QCA6390_PCIE_PCIE_PARF_MHI_BASE_ADDR_LOWER, 0},

	{0, QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_MODE_HANDLER_STATUS, 0},

	{0, QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_MODE_HANDLER_CFG, 0},

	{0, QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2, 0},

	{0, QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_PM_LINKST_IN_L1SUB, 0},

	{0, QCA6390_PCIE_PCIE_CORE_CONFIG, 0},

	{0, QCA6390_PCIE_PCIE_PARF_L1SS_SLEEP_NO_MHI_ACCESS_HANDLER_RD_4, 0},

	{0, QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_PM_LINKST_IN_L2, 0},

	{0, QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_PM_LINKST_IN_L1, 0},

	{0, QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1, 0},

	{0, QCA6390_PCIE_PCIE_PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2, 0},

	{0, QCA6390_PCIE_PCIE_LOCAL_REG_WCSSAON_PCIE_SR_STATUS_HIGH, 0},

	{0, QCA6390_PCIE_PCIE_LOCAL_REG_WCSSAON_PCIE_SR_STATUS_LOW, 0},

	{0, QCA6390_PCIE_PCIE_LOCAL_REG_WCSS_STATUS_FOR_DEBUG_HIGH, 0},

	{0, QCA6390_PCIE_PCIE_LOCAL_REG_WCSS_STATUS_FOR_DEBUG_LOW, 0},

	{0, QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2, 0},

	{0, QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN2_STATUS_REG2, 0},

	{0, QCA6390_WFSS_PMM_WFSS_PMM_R0_PMM_WLAN2_CFG_REG1, 0},

	{0, QCA6390_WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1, 0},

	{0, QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN2_APS_STATUS_REG1, 0},

	{0, QCA6390_WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1, 0},

};



static struct cnss_misc_reg wlaon_reg_access_seq[] = {

	{0, QCA6390_WLAON_WCSSAON_PCIE_SR_STATUS_HI_REG, 0},

	{0, QCA6390_WLAON_SOC_POWER_CTRL, 0},

	{0, QCA6390_WLAON_PCIE_PWR_CTRL_REG, 0},

	{0, QCA6390_WLAON_WCSSAON_PCIE_SR_STATUS_LO_REG, 0},

	{0, QCA6390_WLAON_WCSS_TCSR_PMM_SR_STATUS_HI_REG, 0},

	{0, QCA6390_WLAON_WCSS_TCSR_PMM_SR_STATUS_LO_REG, 0},

	{0, QCA6390_WLAON_SOC_POWER_CTRL, 0},

	{0, QCA6390_WLAON_SOC_PWR_WDG_BARK_THRSHD, 0},

	{0, QCA6390_WLAON_SOC_PWR_WDG_BITE_THRSHD, 0},

	{0, QCA6390_WLAON_SW_COLD_RESET, 0},

	{0, QCA6390_WLAON_RFA_MEM_SLP_NRET_N_OVERRIDE, 0},

	{0, QCA6390_WLAON_GDSC_DELAY_SETTING, 0},

	{0, QCA6390_WLAON_GDSC_DELAY_SETTING2, 0},

	{0, QCA6390_WLAON_WL_PWR_STATUS_REG, 0},

	{0, QCA6390_WLAON_WL_AON_DBG_CFG_REG, 0},

	{0, QCA6390_WLAON_GLOBAL_COUNTER_CTRL1, 0},

	{0, QCA6390_WLAON_GLOBAL_COUNTER_CTRL6, 0},

	{0, QCA6390_WLAON_GLOBAL_COUNTER_CTRL7, 0},

	{0, QCA6390_WLAON_GLOBAL_COUNTER_CTRL3, 0},

	{0, QCA6390_WLAON_GLOBAL_COUNTER_CTRL4, 0},

	{0, QCA6390_WLAON_GLOBAL_COUNTER_CTRL5, 0},

	{0, QCA6390_WLAON_GLOBAL_COUNTER_CTRL8, 0},

	{0, QCA6390_WLAON_GLOBAL_COUNTER_CTRL2, 0},

	{0, QCA6390_WLAON_GLOBAL_COUNTER_CTRL9, 0},

	{0, QCA6390_WLAON_RTC_CLK_CAL_CTRL1, 0},

	{0, QCA6390_WLAON_RTC_CLK_CAL_CTRL2, 0},

	{0, QCA6390_WLAON_RTC_CLK_CAL_CTRL3, 0},

	{0, QCA6390_WLAON_RTC_CLK_CAL_CTRL4, 0},

	{0, QCA6390_WLAON_RTC_CLK_CAL_CTRL5, 0},

	{0, QCA6390_WLAON_RTC_CLK_CAL_CTRL6, 0},

	{0, QCA6390_WLAON_RTC_CLK_CAL_CTRL7, 0},

	{0, QCA6390_WLAON_RTC_CLK_CAL_CTRL8, 0},

	{0, QCA6390_WLAON_RTC_CLK_CAL_CTRL9, 0},

	{0, QCA6390_WLAON_WCSSAON_CONFIG_REG, 0},

	{0, QCA6390_WLAON_WLAN_OEM_DEBUG_REG, 0},

	{0, QCA6390_WLAON_WLAN_RAM_DUMP_REG, 0},

	{0, QCA6390_WLAON_QDSS_WCSS_REG, 0},

	{0, QCA6390_WLAON_QDSS_WCSS_ACK, 0},

	{0, QCA6390_WLAON_WL_CLK_CNTL_KDF_REG, 0},

	{0, QCA6390_WLAON_WL_CLK_CNTL_PMU_HFRC_REG, 0},

	{0, QCA6390_WLAON_QFPROM_PWR_CTRL_REG, 0},

	{0, QCA6390_WLAON_DLY_CONFIG, 0},

	{0, QCA6390_WLAON_WLAON_Q6_IRQ_REG, 0},

	{0, QCA6390_WLAON_PCIE_INTF_SW_CFG_REG, 0},

	{0, QCA6390_WLAON_PCIE_INTF_STICKY_SW_CFG_REG, 0},

	{0, QCA6390_WLAON_PCIE_INTF_PHY_SW_CFG_REG, 0},

	{0, QCA6390_WLAON_PCIE_INTF_PHY_NOCSR_SW_CFG_REG, 0},

	{0, QCA6390_WLAON_Q6_COOKIE_BIT, 0},

	{0, QCA6390_WLAON_WARM_SW_ENTRY, 0},

	{0, QCA6390_WLAON_RESET_DBG_SW_ENTRY, 0},

	{0, QCA6390_WLAON_WL_PMUNOC_CFG_REG, 0},

	{0, QCA6390_WLAON_RESET_CAUSE_CFG_REG, 0},

	{0, QCA6390_WLAON_SOC_WCSSAON_WAKEUP_IRQ_7_EN_REG, 0},

	{0, QCA6390_WLAON_DEBUG, 0},

	{0, QCA6390_WLAON_SOC_PARAMETERS, 0},

	{0, QCA6390_WLAON_WLPM_SIGNAL, 0},

	{0, QCA6390_WLAON_SOC_RESET_CAUSE_REG, 0},

	{0, QCA6390_WLAON_WAKEUP_PCIE_SOC_REG, 0},

	{0, QCA6390_WLAON_PBL_STACK_CANARY, 0},

	{0, QCA6390_WLAON_MEM_TOT_NUM_GRP_REG, 0},

	{0, QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP0_REG, 0},

	{0, QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP1_REG, 0},

	{0, QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP2_REG, 0},

	{0, QCA6390_WLAON_MEM_TOT_BANKS_IN_GRP3_REG, 0},

	{0, QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP0_REG, 0},

	{0, QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP1_REG, 0},

	{0, QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP2_REG, 0},

	{0, QCA6390_WLAON_MEM_TOT_SIZE_IN_GRP3_REG, 0},

	{0, QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP0_REG, 0},

	{0, QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP1_REG, 0},

	{0, QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP2_REG, 0},

	{0, QCA6390_WLAON_MEM_SLP_NRET_OVERRIDE_GRP3_REG, 0},

	{0, QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP0_REG, 0},

	{0, QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP1_REG, 0},

	{0, QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP2_REG, 0},

	{0, QCA6390_WLAON_MEM_SLP_RET_OVERRIDE_GRP3_REG, 0},

	{0, QCA6390_WLAON_MEM_CNT_SEL_REG, 0},

	{0, QCA6390_WLAON_MEM_NO_EXTBHS_REG, 0},

	{0, QCA6390_WLAON_MEM_DEBUG_REG, 0},

	{0, QCA6390_WLAON_MEM_DEBUG_BUS_REG, 0},

	{0, QCA6390_WLAON_MEM_REDUN_CFG_REG, 0},

	{0, QCA6390_WLAON_WL_AON_SPARE2, 0},

	{0, QCA6390_WLAON_VSEL_CFG_FOR_WL_RET_DISABLE_REG, 0},

	{0, QCA6390_WLAON_BTFM_WLAN_IPC_STATUS_REG, 0},

	{0, QCA6390_WLAON_MPM_COUNTER_CHICKEN_BITS, 0},

	{0, QCA6390_WLAON_WLPM_CHICKEN_BITS, 0},

	{0, QCA6390_WLAON_PCIE_PHY_PWR_REG, 0},

	{0, QCA6390_WLAON_WL_CLK_CNTL_PMU_LPO2M_REG, 0},

	{0, QCA6390_WLAON_WL_SS_ROOT_CLK_SWITCH_REG, 0},

	{0, QCA6390_WLAON_POWERCTRL_PMU_REG, 0},

	{0, QCA6390_WLAON_POWERCTRL_MEM_REG, 0},

	{0, QCA6390_WLAON_PCIE_PWR_CTRL_REG, 0},

	{0, QCA6390_WLAON_SOC_PWR_PROFILE_REG, 0},

	{0, QCA6390_WLAON_WCSSAON_PCIE_SR_STATUS_HI_REG, 0},

	{0, QCA6390_WLAON_WCSSAON_PCIE_SR_STATUS_LO_REG, 0},

	{0, QCA6390_WLAON_WCSS_TCSR_PMM_SR_STATUS_HI_REG, 0},

	{0, QCA6390_WLAON_WCSS_TCSR_PMM_SR_STATUS_LO_REG, 0},

	{0, QCA6390_WLAON_MEM_SVS_CFG_REG, 0},

	{0, QCA6390_WLAON_CMN_AON_MISC_REG, 0},

	{0, QCA6390_WLAON_INTR_STATUS, 0},

	{0, QCA6390_SYSPM_SYSPM_PWR_STATUS, 0},

	{0, QCA6390_SYSPM_DBG_BTFM_AON_REG, 0},

	{0, QCA6390_SYSPM_DBG_BUS_SEL_REG, 0},

	{0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0},

	{0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0},

	{0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0},

	{0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0},

	{0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0},

	{0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0},

	{0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0},

	{0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0},

	{0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0},

	{0, QCA6390_SYSPM_WCSSAON_SR_STATUS, 0},

};



#define WCSS_REG_SIZE ARRAY_SIZE(wcss_reg_access_seq)

#define PCIE_REG_SIZE ARRAY_SIZE(pcie_reg_access_seq)

#define WLAON_REG_SIZE ARRAY_SIZE(wlaon_reg_access_seq)



static int cnss_pci_check_link_status(struct cnss_pci_data *pci_priv)

{

	u16 device_id;
@@ -1090,6 +1256,74 @@ int cnss_pci_update_status(struct cnss_pci_data *pci_priv, 
	return 0;

}



static void cnss_pci_misc_reg_dump(struct cnss_pci_data *pci_priv,

				   struct cnss_misc_reg *misc_reg,

				   u32 misc_reg_size,

				   char *reg_name)

{

	int i;



	if (!misc_reg)

		return;



	if (in_interrupt() || irqs_disabled())

		return;



	if (cnss_pci_check_link_status(pci_priv))

		return;



	cnss_pci_force_wake_get(pci_priv);



	cnss_pr_dbg("start to dump %s registers\n", reg_name);



	for (i = 0; i < misc_reg_size; i++) {

		if (misc_reg[i].wr) {

			if (misc_reg[i].offset ==

			    QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_CFG &&

			    i >= 1)

				misc_reg[i].val =

				QCA6390_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_CFG_MSK |

				misc_reg[i - 1].val;

			if (cnss_pci_reg_write(pci_priv,

					       misc_reg[i].offset,

					       misc_reg[i].val))

				goto force_wake_put;

			cnss_pr_vdbg("Write 0x%X to 0x%X\n",

				     misc_reg[i].val,

				     misc_reg[i].offset);



		} else {

			if (cnss_pci_reg_read(pci_priv,

					      misc_reg[i].offset,

					      &misc_reg[i].val))

				goto force_wake_put;

			cnss_pr_vdbg("Read 0x%X from 0x%X\n",

				     misc_reg[i].val,

				     misc_reg[i].offset);

		}

	}



force_wake_put:

	cnss_pci_force_wake_put(pci_priv);

}



static void cnss_pci_dump_misc_reg(struct cnss_pci_data *pci_priv)

{

	if (in_interrupt() || irqs_disabled())

		return;



	if (cnss_pci_check_link_status(pci_priv))

		return;



	mhi_debug_reg_dump(pci_priv->mhi_ctrl);

	cnss_pci_misc_reg_dump(pci_priv, pci_priv->wcss_reg,

			       pci_priv->wcss_reg_size, "wcss");

	cnss_pci_misc_reg_dump(pci_priv, pci_priv->pcie_reg,

			       pci_priv->pcie_reg_size, "pcie");

	cnss_pci_misc_reg_dump(pci_priv, pci_priv->wlaon_reg,

			       pci_priv->wlaon_reg_size, "wlaon");

}



static void cnss_pci_dump_shadow_reg(struct cnss_pci_data *pci_priv)

{

	int i, j = 0, array_size = SHADOW_REG_COUNT + SHADOW_REG_INTER_COUNT;
@@ -2537,6 +2771,7 @@ int cnss_pci_force_fw_assert_hdlr(struct cnss_pci_data *pci_priv) 
		return -ENODEV;



	cnss_auto_resume(&pci_priv->pci_dev->dev);

	cnss_pci_dump_misc_reg(pci_priv);

	cnss_pci_dump_shadow_reg(pci_priv);



	ret = cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_TRIGGER_RDDM);
@@ -3073,6 +3308,7 @@ void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv, bool in_panic) 
	if (cnss_pci_check_link_status(pci_priv))

		return;



	cnss_pci_dump_misc_reg(pci_priv);

	cnss_pci_dump_qdss_reg(pci_priv);



	ret = mhi_download_rddm_img(pci_priv->mhi_ctrl, in_panic);
@@ -3392,6 +3628,31 @@ static void cnss_pci_unregister_mhi(struct cnss_pci_data *pci_priv) 
	kfree(mhi_ctrl->irq);

}



static void cnss_pci_config_regs(struct cnss_pci_data *pci_priv)

{

	switch (pci_priv->device_id) {

	case QCA6390_DEVICE_ID:

		pci_priv->wcss_reg = wcss_reg_access_seq;

		pci_priv->wcss_reg_size = WCSS_REG_SIZE;

		pci_priv->pcie_reg = pcie_reg_access_seq;

		pci_priv->pcie_reg_size = PCIE_REG_SIZE;

		pci_priv->wlaon_reg = wlaon_reg_access_seq;

		pci_priv->wlaon_reg_size = WLAON_REG_SIZE;



		/* Configure WDOG register with specific value so that we can

		 * know if HW is in the process of WDOG reset recovery or not

		 * when reading the registers.

		 */

		cnss_pci_reg_write

		(pci_priv,

		QCA6390_PCIE_SOC_WDOG_DISC_BAD_DATA_LOW_CFG_SOC_PCIE_REG,

		QCA6390_PCIE_SOC_WDOG_DISC_BAD_DATA_LOW_CFG_SOC_PCIE_REG_VAL);

		break;

	default:

		return;

	}

}



static int cnss_pci_probe(struct pci_dev *pci_dev,

			  const struct pci_device_id *id)

{
@@ -3473,6 +3734,9 @@ static int cnss_pci_probe(struct pci_dev *pci_dev, 
			goto disable_bus;

		}

		cnss_pci_get_link_status(pci_priv);



		cnss_pci_config_regs(pci_priv);



		if (EMULATION_HW)

			break;

		ret = cnss_suspend_pci_link(pci_priv);

drivers/net/wireless/cnss2/pci.h

+12 −0
Original line number Diff line number Diff line
@@ -53,6 +53,12 @@ struct cnss_pci_debug_reg { 
	u32 val;

};



struct cnss_misc_reg {

	u8 wr;

	u32 offset;

	u32 val;

};



struct cnss_pci_data {

	struct pci_dev *pci_dev;

	struct cnss_plat_data *plat_priv;
@@ -87,6 +93,12 @@ struct cnss_pci_data { 
	struct delayed_work time_sync_work;

	u8 disable_pc;

	struct cnss_pci_debug_reg *debug_reg;

	struct cnss_misc_reg *wcss_reg;

	u32 wcss_reg_size;

	struct cnss_misc_reg *pcie_reg;

	u32 pcie_reg_size;

	struct cnss_misc_reg *wlaon_reg;

	u32 wlaon_reg_size;

};



static inline void cnss_set_pci_priv(struct pci_dev *pci_dev, void *data)

drivers/net/wireless/cnss2/reg.h

0 → 100644
+267 −0

File added.

Preview size limit exceeded, changes collapsed.