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Commit ad1a7d20 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Update the GGTT size/alignment query functions 



In order to be consistent with other address space functions, we want to
pass around 64-bit sizes, even though all known global GTT are limited
to 4GiB. Similarly, we are trying to be consistent in using the _ggtt_
nomenclature when referring to the special global GTT.

v2: Update docs to consistently state "global GTT".

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1470324762-2545-11-git-send-email-chris@chris-wilson.co.uk
parent 954c4691

drivers/gpu/drm/i915/i915_drv.h

+3 −5
Original line number Diff line number Diff line
@@ -3241,10 +3241,8 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, 
int i915_gem_open(struct drm_device *dev, struct drm_file *file);

void i915_gem_release(struct drm_device *dev, struct drm_file *file);



uint32_t

i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);

uint32_t

i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,

u64 i915_gem_get_ggtt_size(struct drm_device *dev, u64 size, int tiling_mode);

u64 i915_gem_get_ggtt_alignment(struct drm_device *dev, u64 size,

				int tiling_mode, bool fenced);



int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,

drivers/gpu/drm/i915/i915_gem.c

+46 −35
Original line number Diff line number Diff line
@@ -1847,46 +1847,57 @@ i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) 
		i915_gem_release_mmap(obj);

}



uint32_t

i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)

/**

 * i915_gem_get_ggtt_size - return required global GTT size for an object

 * @dev: drm device

 * @size: object size

 * @tiling_mode: tiling mode

 *

 * Return the required global GTT size for an object, taking into account

 * potential fence register mapping.

 */

u64 i915_gem_get_ggtt_size(struct drm_device *dev, u64 size, int tiling_mode)

{

	uint32_t gtt_size;

	u64 ggtt_size;



	if (INTEL_INFO(dev)->gen >= 4 ||

	GEM_BUG_ON(size == 0);



	if (INTEL_GEN(dev) >= 4 ||

	    tiling_mode == I915_TILING_NONE)

		return size;



	/* Previous chips need a power-of-two fence region when tiling */

	if (IS_GEN3(dev))

		gtt_size = 1024*1024;

		ggtt_size = 1024*1024;

	else

		gtt_size = 512*1024;

		ggtt_size = 512*1024;



	while (gtt_size < size)

		gtt_size <<= 1;

	while (ggtt_size < size)

		ggtt_size <<= 1;



	return gtt_size;

	return ggtt_size;

}



/**

 * i915_gem_get_gtt_alignment - return required GTT alignment for an object

 * i915_gem_get_ggtt_alignment - return required global GTT alignment

 * @dev: drm device

 * @size: object size

 * @tiling_mode: tiling mode

 * @fenced: is fenced alignemned required or not

 * @fenced: is fenced alignment required or not

 *

 * Return the required GTT alignment for an object, taking into account

 * Return the required global GTT alignment for an object, taking into account

 * potential fence register mapping.

 */

uint32_t

i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,

u64 i915_gem_get_ggtt_alignment(struct drm_device *dev, u64 size,

				int tiling_mode, bool fenced)

{

	GEM_BUG_ON(size == 0);



	/*

	 * Minimum alignment is 4k (GTT page size), but might be greater

	 * if a fence register is needed for the object.

	 */

	if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||

	if (INTEL_GEN(dev) >= 4 || (!fenced && IS_G33(dev)) ||

	    tiling_mode == I915_TILING_NONE)

		return 4096;
@@ -1894,7 +1905,7 @@ i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, 
	 * Previous chips need to be aligned to the size of the smallest

	 * fence register that can contain the object.

	 */

	return i915_gem_get_gtt_size(dev, size, tiling_mode);

	return i915_gem_get_ggtt_size(dev, size, tiling_mode);

}



static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
@@ -2984,14 +2995,14 @@ i915_gem_object_insert_into_vm(struct drm_i915_gem_object *obj, 


		view_size = i915_ggtt_view_size(obj, ggtt_view);



		fence_size = i915_gem_get_gtt_size(dev,

		fence_size = i915_gem_get_ggtt_size(dev,

						    view_size,

						    obj->tiling_mode);

		fence_alignment = i915_gem_get_gtt_alignment(dev,

		fence_alignment = i915_gem_get_ggtt_alignment(dev,

							      view_size,

							      obj->tiling_mode,

							      true);

		unfenced_alignment = i915_gem_get_gtt_alignment(dev,

		unfenced_alignment = i915_gem_get_ggtt_alignment(dev,

								 view_size,

								 obj->tiling_mode,

								 false);
@@ -3698,10 +3709,10 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) 
	bool mappable, fenceable;

	u32 fence_size, fence_alignment;



	fence_size = i915_gem_get_gtt_size(obj->base.dev,

	fence_size = i915_gem_get_ggtt_size(obj->base.dev,

					    obj->base.size,

					    obj->tiling_mode);

	fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,

	fence_alignment = i915_gem_get_ggtt_alignment(obj->base.dev,

						      obj->base.size,

						      obj->tiling_mode,

						      true);

drivers/gpu/drm/i915/i915_gem_tiling.c

+2 −1
Original line number Diff line number Diff line
@@ -133,7 +133,8 @@ i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode) 
			return false;

	}



	size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode);

	size = i915_gem_get_ggtt_size(obj->base.dev,

				      obj->base.size, tiling_mode);

	if (i915_gem_obj_ggtt_size(obj) != size)

		return false;