Merge branch 'macb-coding-style'

#define MACB_WOL_HAS_MAGIC_PACKET	(0x1 << 0)

#define MACB_WOL_ENABLED		(0x1 << 1)

/*

 * Graceful stop timeouts in us. We should allow up to

/* Graceful stop timeouts in us. We should allow up to

 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)

 */

#define MACB_HALT_TIMEOUT	1230

	writel_relaxed(value, bp->regs + offset);

}

/*

 * Find the CPU endianness by using the loopback bit of NCR register. When the

 * CPU is in big endian we need to program swaped mode for management

/* Find the CPU endianness by using the loopback bit of NCR register. When the

 * CPU is in big endian we need to program swapped mode for management

 * descriptor access.

 */

static bool hw_is_native_io(void __iomem *addr)

	pdata = dev_get_platdata(&bp->pdev->dev);

	/* Check all 4 address register for vaild address */

	/* Check all 4 address register for valid address */

	for (i = 0; i < 4; i++) {

		bottom = macb_or_gem_readl(bp, SA1B + i * 8);

		top = macb_or_gem_readl(bp, SA1T + i * 8);

	pdata = dev_get_platdata(&bp->pdev->dev);

	if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {

		ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");

		ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin,

					"phy int");

		if (!ret) {

			phy_irq = gpio_to_irq(pdata->phy_irq_pin);

			phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;

	macb_writel(bp, NCR, MACB_BIT(MPE));

	bp->mii_bus = mdiobus_alloc();

	if (bp->mii_bus == NULL) {

	if (!bp->mii_bus) {

		err = -ENOMEM;

		goto err_out;

	}

		err = of_mdiobus_register(bp->mii_bus, np);

		/* fallback to standard phy registration if no phy were

		   found during dt phy registration */

		 * found during dt phy registration

		 */

		if (!err && !phy_find_first(bp->mii_bus)) {

			for (i = 0; i < PHY_MAX_ADDR; i++) {

				struct phy_device *phydev;

	/* Make sure nobody is trying to queue up new packets */

	netif_tx_stop_all_queues(bp->dev);

	/*

	 * Stop transmission now

	/* Stop transmission now

	 * (in case we have just queued new packets)

	 * macb/gem must be halted to write TBQP register

	 */

		/* Just complain for now, reinitializing TX path can be good */

		netdev_err(bp->dev, "BUG: halt tx timed out\n");

	/*

	 * Treat frames in TX queue including the ones that caused the error.

	/* Treat frames in TX queue including the ones that caused the error.

	 * Free transmit buffers in upper layer.

	 */

	for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {

				bp->stats.tx_bytes += skb->len;

			}

		} else {

			/*

			 * "Buffers exhausted mid-frame" errors may only happen

			 * if the driver is buggy, so complain loudly about those.

			 * Statistics are updated by hardware.

			/* "Buffers exhausted mid-frame" errors may only happen

			 * if the driver is buggy, so complain loudly about

			 * those. Statistics are updated by hardware.

			 */

			if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))

				netdev_err(bp->dev,

	struct sk_buff		*skb;

	dma_addr_t		paddr;

	while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {

	while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail,

			  RX_RING_SIZE) > 0) {

		entry = macb_rx_ring_wrap(bp->rx_prepared_head);

		/* Make hw descriptor updates visible to CPU */

		bp->rx_prepared_head++;

		if (bp->rx_skbuff[entry] == NULL) {

		if (!bp->rx_skbuff[entry]) {

			/* allocate sk_buff for this free entry in ring */

			skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);

			if (unlikely(skb == NULL)) {

			if (unlikely(!skb)) {

				netdev_err(bp->dev,

					   "Unable to allocate sk_buff\n");

				break;

			/* now fill corresponding descriptor entry */

			paddr = dma_map_single(&bp->pdev->dev, skb->data,

					       bp->rx_buffer_size, DMA_FROM_DEVICE);

					       bp->rx_buffer_size,

					       DMA_FROM_DEVICE);

			if (dma_mapping_error(&bp->pdev->dev, paddr)) {

				dev_kfree_skb(skb);

				break;

	for (frag = begin; frag != end; frag++) {

		struct macb_dma_desc *desc = macb_rx_desc(bp, frag);

		desc->addr &= ~MACB_BIT(RX_USED);

	}

	/* Make descriptor updates visible to hardware */

	wmb();

	/*

	 * When this happens, the hardware stats registers for

	/* When this happens, the hardware stats registers for

	 * whatever caused this is updated, so we don't have to record

	 * anything.

	 */

		    macb_rx_ring_wrap(first_frag),

		    macb_rx_ring_wrap(last_frag), len);

	/*

	 * The ethernet header starts NET_IP_ALIGN bytes into the

	/* The ethernet header starts NET_IP_ALIGN bytes into the

	 * first buffer. Since the header is 14 bytes, this makes the

	 * payload word-aligned.

	 *

			frag_len = len - offset;

		}

		skb_copy_to_linear_data_offset(skb, offset,

				macb_rx_buffer(bp, frag), frag_len);

					       macb_rx_buffer(bp, frag),

					       frag_len);

		offset += bp->rx_buffer_size;

		desc = macb_rx_desc(bp, frag);

		desc->addr &= ~MACB_BIT(RX_USED);

			    (unsigned long)status);

		if (status & MACB_RX_INT_FLAGS) {

			/*

			 * There's no point taking any more interrupts

			/* There's no point taking any more interrupts

			 * until we have processed the buffers. The

			 * scheduling call may fail if the poll routine

			 * is already scheduled, so disable interrupts

		if (status & MACB_BIT(TCOMP))

			macb_tx_interrupt(queue);

		/*

		 * Link change detection isn't possible with RMII, so we'll

		/* Link change detection isn't possible with RMII, so we'll

		 * add that if/when we get our hands on a full-blown MII PHY.

		 */

		}

		if (status & MACB_BIT(HRESP)) {

			/*

			 * TODO: Reset the hardware, and maybe move the

			/* TODO: Reset the hardware, and maybe move the

			 * netdev_err to a lower-priority context as well

			 * (work queue?)

			 */

}

#ifdef CONFIG_NET_POLL_CONTROLLER

/*

 * Polling receive - used by netconsole and other diagnostic tools

/* Polling receive - used by netconsole and other diagnostic tools

 * to allow network i/o with interrupts disabled.

 */

static void macb_poll_controller(struct net_device *dev)

	}

	/* Should never happen */

	if (unlikely(tx_skb == NULL)) {

	if (unlikely(!tx_skb)) {

		netdev_err(bp->dev, "BUG! empty skb!\n");

		return 0;

	}

	/* Count how many TX buffer descriptors are needed to send this

	 * socket buffer: skb fragments of jumbo frames may need to be

	 * splitted into many buffer descriptors.

	 * split into many buffer descriptors.

	 */

	count = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);

	nr_frags = skb_shinfo(skb)->nr_frags;

	for (i = 0; i < RX_RING_SIZE; i++) {

		skb = bp->rx_skbuff[i];

		if (skb == NULL)

		if (!skb)

			continue;

		desc = &bp->rx_ring[i];

	bp->rx_skbuff = kzalloc(size, GFP_KERNEL);

	if (!bp->rx_skbuff)

		return -ENOMEM;

	else

	netdev_dbg(bp->dev,

		   "Allocated %d RX struct sk_buff entries at %p\n",

		   RX_RING_SIZE, bp->rx_skbuff);

					    &bp->rx_buffers_dma, GFP_KERNEL);

	if (!bp->rx_buffers)

		return -ENOMEM;

	else

	netdev_dbg(bp->dev,

		   "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",

		   size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);

	struct macb_queue *queue;

	unsigned int q;

	/*

	 * Disable RX and TX (XXX: Should we halt the transmission

	/* Disable RX and TX (XXX: Should we halt the transmission

	 * more gracefully?)

	 */

	macb_writel(bp, NCR, 0);

	return config;

}

/*

 * Get the DMA bus width field of the network configuration register that we

/* Get the DMA bus width field of the network configuration register that we

 * should program.  We find the width from decoding the design configuration

 * register to find the maximum supported data bus width.

 */

	}

}

/*

 * Configure the receive DMA engine

/* Configure the receive DMA engine

 * - use the correct receive buffer size

 * - set best burst length for DMA operations

 *   (if not supported by FIFO, it will fallback to default)

	macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));

}

/*

 * The hash address register is 64 bits long and takes up two

/* The hash address register is 64 bits long and takes up two

 * locations in the memory map.  The least significant bits are stored

 * in EMAC_HSL and the most significant bits in EMAC_HSH.

 *

	return 0;

}

/*

 * Return the hash index value for the specified address.

 */

/* Return the hash index value for the specified address. */

static int hash_get_index(__u8 *addr)

{

	int i, j, bitval;

	return hash_index;

}

/*

 * Add multicast addresses to the internal multicast-hash table.

 */

/* Add multicast addresses to the internal multicast-hash table. */

static void macb_sethashtable(struct net_device *dev)

{

	struct netdev_hw_addr *ha;

	unsigned int bitnr;

	struct macb *bp = netdev_priv(dev);

	mc_filter[0] = mc_filter[1] = 0;

	mc_filter[0] = 0;

	mc_filter[1] = 0;

	netdev_for_each_mc_addr(ha, dev) {

		bitnr = hash_get_index(ha->addr);

	macb_or_gem_writel(bp, HRT, mc_filter[1]);

}

/*

 * Enable/Disable promiscuous and multicast modes.

 */

/* Enable/Disable promiscuous and multicast modes. */

static void macb_set_rx_mode(struct net_device *dev)

{

	unsigned long cfg;

	if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))

		regs_buff[12] = macb_or_gem_readl(bp, USRIO);

	if (macb_is_gem(bp)) {

	if (macb_is_gem(bp))

		regs_buff[13] = gem_readl(bp, DMACFG);

}

}

static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)

{

	.ndo_set_features	= macb_set_features,

};

/*

 * Configure peripheral capabilities according to device tree

/* Configure peripheral capabilities according to device tree

 * and integration options used

 */

static void macb_configure_caps(struct macb *bp, const struct macb_config *dt_conf)

static void macb_configure_caps(struct macb *bp,

				const struct macb_config *dt_conf)

{

	u32 dcfg;

	mac = of_get_mac_address(np);

	if (mac)

		memcpy(bp->dev->dev_addr, mac, ETH_ALEN);

		ether_addr_copy(bp->dev->dev_addr, mac);

	else

		macb_get_hwaddr(bp);

	phy_node =  of_get_next_available_child(np, NULL);

	if (phy_node) {

		int gpio = of_get_named_gpio(phy_node, "reset-gpios", 0);

		if (gpio_is_valid(gpio)) {

			bp->reset_gpio = gpio_to_desc(gpio);

			gpiod_direction_output(bp->reset_gpio, 1);