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Commit acb32506 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie
Browse files

drm/radeon/kms: improve pflip precision on r1xx-r4xx 



The update pending bit has a separate enable bit.

Cc: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
Signed-off-by: default avatarAlex Deucher <alexdeucher@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent b6724405

drivers/gpu/drm/radeon/r100.c

+5 −3
Original line number Diff line number Diff line
@@ -76,6 +76,8 @@ void r100_pre_page_flip(struct radeon_device *rdev, int crtc) 
	/* make sure flip is at vb rather than hb */

	tmp = RREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset);

	tmp &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;

	/* make sure pending bit is asserted */

	tmp |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;

	WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, tmp);



	/* set pageflip to happen as late as possible in the vblank interval.
@@ -104,9 +106,9 @@ u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 
	/* update the scanout addresses */

	WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);



	/* Note: We don't wait for update_pending to assert, as this never

	 * happens for some reason on R1xx - R4xx. Adds a bit of imprecision.

	 */

	/* Wait for update_pending to go high. */

	while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET));

	DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");



	/* Unlock the lock, so double-buffering can take place inside vblank */

	tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;

drivers/gpu/drm/radeon/radeon_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -510,6 +510,8 @@ 
#       define RADEON_CRTC_TILE_EN                      (1 << 15)

#       define RADEON_CRTC_OFFSET_FLIP_CNTL             (1 << 16)

#       define RADEON_CRTC_STEREO_OFFSET_EN             (1 << 17)

#       define RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN      (1 << 28)

#       define RADEON_CRTC_GUI_TRIG_OFFSET_RIGHT_EN     (1 << 29)



#define R300_CRTC_TILE_X0_Y0	            0x0350

#define R300_CRTC2_TILE_X0_Y0	            0x0358