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Commit acb20054 authored by Michael Chan's avatar Michael Chan Committed by David S. Miller
Browse files

bnxt_en: Update firmware interface spec to 1.8.0. 



VF representors and PTP are added features in the new firmware spec.

Signed-off-by: default avatarMichael Chan <michael.chan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e42e24c3

drivers/net/ethernet/broadcom/bnxt/bnxt.c

+5 −3
Original line number Diff line number Diff line
@@ -5646,7 +5646,7 @@ static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) 
	if (rc)

		goto hwrm_phy_qcaps_exit;



	if (resp->eee_supported & PORT_PHY_QCAPS_RESP_EEE_SUPPORTED) {

	if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {

		struct ethtool_eee *eee = &bp->eee;

		u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
@@ -5686,13 +5686,15 @@ static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) 


	memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));

	link_info->phy_link_status = resp->link;

	link_info->duplex =  resp->duplex;

	link_info->duplex = resp->duplex_cfg;

	if (bp->hwrm_spec_code >= 0x10800)

		link_info->duplex = resp->duplex_state;

	link_info->pause = resp->pause;

	link_info->auto_mode = resp->auto_mode;

	link_info->auto_pause_setting = resp->auto_pause;

	link_info->lp_pause = resp->link_partner_adv_pause;

	link_info->force_pause_setting = resp->force_pause;

	link_info->duplex_setting = resp->duplex;

	link_info->duplex_setting = resp->duplex_cfg;

	if (link_info->phy_link_status == BNXT_LINK_LINK)

		link_info->link_speed = le16_to_cpu(resp->link_speed);

	else

drivers/net/ethernet/broadcom/bnxt/bnxt.h

+4 −4
Original line number Diff line number Diff line
@@ -12,10 +12,10 @@ 
#define BNXT_H



#define DRV_MODULE_NAME		"bnxt_en"

#define DRV_MODULE_VERSION	"1.7.0"

#define DRV_MODULE_VERSION	"1.8.0"



#define DRV_VER_MAJ	1

#define DRV_VER_MIN	7

#define DRV_VER_MIN	8

#define DRV_VER_UPD	0



#include <linux/interrupt.h>
@@ -825,8 +825,8 @@ struct bnxt_link_info { 
	u8			loop_back;

	u8			link_up;

	u8			duplex;

#define BNXT_LINK_DUPLEX_HALF	PORT_PHY_QCFG_RESP_DUPLEX_HALF

#define BNXT_LINK_DUPLEX_FULL	PORT_PHY_QCFG_RESP_DUPLEX_FULL

#define BNXT_LINK_DUPLEX_HALF	PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF

#define BNXT_LINK_DUPLEX_FULL	PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL

	u8			pause;

#define BNXT_LINK_PAUSE_TX	PORT_PHY_QCFG_RESP_PAUSE_TX

#define BNXT_LINK_PAUSE_RX	PORT_PHY_QCFG_RESP_PAUSE_RX

drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h

+293 −29
Original line number Diff line number Diff line
@@ -11,14 +11,14 @@ 
#ifndef BNXT_HSI_H

#define BNXT_HSI_H



/* HSI and HWRM Specification 1.7.6 */

/* HSI and HWRM Specification 1.8.0 */

#define HWRM_VERSION_MAJOR	1

#define HWRM_VERSION_MINOR	7

#define HWRM_VERSION_UPDATE	6

#define HWRM_VERSION_MINOR	8

#define HWRM_VERSION_UPDATE	0



#define HWRM_VERSION_RSVD	2 /* non-zero means beta version */

#define HWRM_VERSION_RSVD	0 /* non-zero means beta version */



#define HWRM_VERSION_STR	"1.7.6.2"

#define HWRM_VERSION_STR	"1.8.0.0"

/*

 * Following is the signature for HWRM message field that indicates not

 * applicable (All F's). Need to cast it the size of the field if needed.
@@ -835,9 +835,8 @@ struct hwrm_func_qcfg_output { 
	u8 port_pf_cnt;

	#define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL		   0x0UL

	__le16 dflt_vnic_id;

	u8 host_cnt;

	#define FUNC_QCFG_RESP_HOST_CNT_UNAVAIL		   0x0UL

	u8 unused_0;

	u8 unused_1;

	__le32 min_bw;

	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK		    0xfffffffUL

	#define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT		    0
@@ -874,12 +873,56 @@ struct hwrm_func_qcfg_output { 
	#define FUNC_QCFG_RESP_EVB_MODE_NO_EVB			   0x0UL

	#define FUNC_QCFG_RESP_EVB_MODE_VEB			   0x1UL

	#define FUNC_QCFG_RESP_EVB_MODE_VEPA			   0x2UL

	u8 unused_1;

	u8 unused_2;

	__le16 alloc_vfs;

	__le32 alloc_mcast_filters;

	__le32 alloc_hw_ring_grps;

	__le16 alloc_sp_tx_rings;

	u8 unused_3;

	u8 valid;

};



/* hwrm_func_vlan_cfg */

/* Input (48 bytes) */

struct hwrm_func_vlan_cfg_input {

	__le16 req_type;

	__le16 cmpl_ring;

	__le16 seq_id;

	__le16 target_id;

	__le64 resp_addr;

	__le16 fid;

	u8 unused_0;

	u8 unused_1;

	__le32 enables;

	#define FUNC_VLAN_CFG_REQ_ENABLES_STAG_VID		    0x1UL

	#define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_VID		    0x2UL

	#define FUNC_VLAN_CFG_REQ_ENABLES_STAG_PCP		    0x4UL

	#define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_PCP		    0x8UL

	#define FUNC_VLAN_CFG_REQ_ENABLES_STAG_TPID		    0x10UL

	#define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_TPID		    0x20UL

	__le16 stag_vid;

	u8 stag_pcp;

	u8 unused_2;

	__be16 stag_tpid;

	__le16 ctag_vid;

	u8 ctag_pcp;

	u8 unused_3;

	__be16 ctag_tpid;

	__le32 rsvd1;

	__le32 rsvd2;

	__le32 unused_4;

};



/* Output (16 bytes) */

struct hwrm_func_vlan_cfg_output {

	__le16 error_code;

	__le16 req_type;

	__le16 seq_id;

	__le16 resp_len;

	__le32 unused_0;

	u8 unused_1;

	u8 unused_2;

	u8 unused_3;

	u8 valid;

};
@@ -902,6 +945,7 @@ struct hwrm_func_cfg_input { 
	#define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE	    0x200UL

	#define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE	    0x400UL

	#define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST		    0x800UL

	#define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC	    0x1000UL

	__le32 enables;

	#define FUNC_CFG_REQ_ENABLES_MTU			    0x1UL

	#define FUNC_CFG_REQ_ENABLES_MRU			    0x2UL
@@ -1456,9 +1500,9 @@ struct hwrm_port_phy_qcfg_output { 
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB		   0x1f4UL

	#define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB		   0x3e8UL

	#define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB		   0xffffUL

	u8 duplex;

	#define PORT_PHY_QCFG_RESP_DUPLEX_HALF			   0x0UL

	#define PORT_PHY_QCFG_RESP_DUPLEX_FULL			   0x1UL

	u8 duplex_cfg;

	#define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF		   0x0UL

	#define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL		   0x1UL

	u8 pause;

	#define PORT_PHY_QCFG_RESP_PAUSE_TX			    0x1UL

	#define PORT_PHY_QCFG_RESP_PAUSE_RX			    0x2UL
@@ -1573,6 +1617,9 @@ struct hwrm_port_phy_qcfg_output { 
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4	   0x16UL

	#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4	   0x17UL

	#define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE      0x18UL

	#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET		   0x19UL

	#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX		   0x1aUL

	#define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX		   0x1bUL

	u8 media_type;

	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN		   0x0UL

	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP		   0x1UL
@@ -1651,14 +1698,16 @@ struct hwrm_port_phy_qcfg_output { 
	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED    0x10UL

	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED  0x20UL

	#define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED    0x40UL

	u8 duplex_state;

	#define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF		   0x0UL

	#define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL		   0x1UL

	u8 unused_1;

	u8 unused_2;

	char phy_vendor_name[16];

	char phy_vendor_partnumber[16];

	__le32 unused_3;

	__le32 unused_2;

	u8 unused_3;

	u8 unused_4;

	u8 unused_5;

	u8 unused_6;

	u8 valid;

};
@@ -1744,6 +1793,51 @@ struct hwrm_port_mac_cfg_output { 
	u8 valid;

};



/* hwrm_port_mac_ptp_qcfg */

/* Input (24 bytes) */

struct hwrm_port_mac_ptp_qcfg_input {

	__le16 req_type;

	__le16 cmpl_ring;

	__le16 seq_id;

	__le16 target_id;

	__le64 resp_addr;

	__le16 port_id;

	__le16 unused_0[3];

};



/* Output (80 bytes) */

struct hwrm_port_mac_ptp_qcfg_output {

	__le16 error_code;

	__le16 req_type;

	__le16 seq_id;

	__le16 resp_len;

	u8 flags;

	#define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS	    0x1UL

	#define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS	    0x2UL

	u8 unused_0;

	__le16 unused_1;

	__le32 rx_ts_reg_off_lower;

	__le32 rx_ts_reg_off_upper;

	__le32 rx_ts_reg_off_seq_id;

	__le32 rx_ts_reg_off_src_id_0;

	__le32 rx_ts_reg_off_src_id_1;

	__le32 rx_ts_reg_off_src_id_2;

	__le32 rx_ts_reg_off_domain_id;

	__le32 rx_ts_reg_off_fifo;

	__le32 rx_ts_reg_off_fifo_adv;

	__le32 rx_ts_reg_off_granularity;

	__le32 tx_ts_reg_off_lower;

	__le32 tx_ts_reg_off_upper;

	__le32 tx_ts_reg_off_seq_id;

	__le32 tx_ts_reg_off_fifo;

	__le32 tx_ts_reg_off_granularity;

	__le32 unused_2;

	u8 unused_3;

	u8 unused_4;

	u8 unused_5;

	u8 valid;

};



/* hwrm_port_qstats */

/* Input (40 bytes) */

struct hwrm_port_qstats_input {
@@ -1874,10 +1968,10 @@ struct hwrm_port_phy_qcaps_output { 
	__le16 req_type;

	__le16 seq_id;

	__le16 resp_len;

	u8 eee_supported;

	#define PORT_PHY_QCAPS_RESP_EEE_SUPPORTED		    0x1UL

	#define PORT_PHY_QCAPS_RESP_RSVD1_MASK			    0xfeUL

	#define PORT_PHY_QCAPS_RESP_RSVD1_SFT			    1

	u8 flags;

	#define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED	    0x1UL

	#define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK		    0xfeUL

	#define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT		    1

	u8 unused_0;

	__le16 supported_speeds_force_mode;

	#define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL
@@ -3152,6 +3246,95 @@ struct hwrm_queue_cos2bw_cfg_output { 
	u8 valid;

};



/* hwrm_queue_dscp_qcaps */

/* Input (24 bytes) */

struct hwrm_queue_dscp_qcaps_input {

	__le16 req_type;

	__le16 cmpl_ring;

	__le16 seq_id;

	__le16 target_id;

	__le64 resp_addr;

	u8 port_id;

	u8 unused_0[7];

};



/* Output (16 bytes) */

struct hwrm_queue_dscp_qcaps_output {

	__le16 error_code;

	__le16 req_type;

	__le16 seq_id;

	__le16 resp_len;

	u8 num_dscp_bits;

	u8 unused_0;

	__le16 max_entries;

	u8 unused_1;

	u8 unused_2;

	u8 unused_3;

	u8 valid;

};



/* hwrm_queue_dscp2pri_qcfg */

/* Input (32 bytes) */

struct hwrm_queue_dscp2pri_qcfg_input {

	__le16 req_type;

	__le16 cmpl_ring;

	__le16 seq_id;

	__le16 target_id;

	__le64 resp_addr;

	__le64 dest_data_addr;

	u8 port_id;

	u8 unused_0;

	__le16 dest_data_buffer_size;

	__le32 unused_1;

};



/* Output (16 bytes) */

struct hwrm_queue_dscp2pri_qcfg_output {

	__le16 error_code;

	__le16 req_type;

	__le16 seq_id;

	__le16 resp_len;

	__le16 entry_cnt;

	u8 default_pri;

	u8 unused_0;

	u8 unused_1;

	u8 unused_2;

	u8 unused_3;

	u8 valid;

};



/* hwrm_queue_dscp2pri_cfg */

/* Input (40 bytes) */

struct hwrm_queue_dscp2pri_cfg_input {

	__le16 req_type;

	__le16 cmpl_ring;

	__le16 seq_id;

	__le16 target_id;

	__le64 resp_addr;

	__le64 src_data_addr;

	__le32 flags;

	#define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI    0x1UL

	__le32 enables;

	#define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI	    0x1UL

	u8 port_id;

	u8 default_pri;

	__le16 entry_cnt;

	__le32 unused_0;

};



/* Output (16 bytes) */

struct hwrm_queue_dscp2pri_cfg_output {

	__le16 error_code;

	__le16 req_type;

	__le16 seq_id;

	__le16 resp_len;

	__le32 unused_0;

	u8 unused_1;

	u8 unused_2;

	u8 unused_3;

	u8 valid;

};



/* hwrm_vnic_alloc */

/* Input (24 bytes) */

struct hwrm_vnic_alloc_input {
@@ -4038,7 +4221,7 @@ struct hwrm_cfa_encap_record_alloc_input { 
	#define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE       0x8UL

	u8 unused_0;

	__le16 unused_1;

	__le32 encap_data[16];

	__le32 encap_data[20];

};



/* Output (16 bytes) */
@@ -4120,8 +4303,8 @@ struct hwrm_cfa_ntuple_filter_alloc_input { 
	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6     0x6UL

	u8 ip_protocol;

	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN   0x0UL

	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP       0x6UL

	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP       0x11UL

	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP       0x6UL

	#define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP       0x11UL

	__le16 dst_id;

	__le16 mirror_vnic_id;

	u8 tunnel_type;
@@ -4224,6 +4407,58 @@ struct hwrm_cfa_ntuple_filter_cfg_output { 
	u8 valid;

};



/* hwrm_cfa_vfr_alloc */

/* Input (32 bytes) */

struct hwrm_cfa_vfr_alloc_input {

	__le16 req_type;

	__le16 cmpl_ring;

	__le16 seq_id;

	__le16 target_id;

	__le64 resp_addr;

	__le16 vf_id;

	__le16 reserved;

	__le32 unused_0;

	char vfr_name[32];

};



/* Output (16 bytes) */

struct hwrm_cfa_vfr_alloc_output {

	__le16 error_code;

	__le16 req_type;

	__le16 seq_id;

	__le16 resp_len;

	__le16 rx_cfa_code;

	__le16 tx_cfa_action;

	u8 unused_0;

	u8 unused_1;

	u8 unused_2;

	u8 valid;

};



/* hwrm_cfa_vfr_free */

/* Input (24 bytes) */

struct hwrm_cfa_vfr_free_input {

	__le16 req_type;

	__le16 cmpl_ring;

	__le16 seq_id;

	__le16 target_id;

	__le64 resp_addr;

	char vfr_name[32];

};



/* Output (16 bytes) */

struct hwrm_cfa_vfr_free_output {

	__le16 error_code;

	__le16 req_type;

	__le16 seq_id;

	__le16 resp_len;

	__le32 unused_0;

	u8 unused_1;

	u8 unused_2;

	u8 unused_3;

	u8 valid;

};



/* hwrm_tunnel_dst_port_query */

/* Input (24 bytes) */

struct hwrm_tunnel_dst_port_query_input {
@@ -4448,12 +4683,13 @@ struct hwrm_fw_reset_input { 
	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT		   0x1UL

	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL	   0x2UL

	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE		   0x3UL

	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_RSVD		   0x4UL

	#define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST		   0x4UL

	u8 selfrst_status;

	#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE	   0x0UL

	#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP	   0x1UL

	#define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST	   0x2UL

	__le16 unused_0[3];

	u8 host_idx;

	u8 unused_0[5];

};



/* Output (16 bytes) */
@@ -4487,7 +4723,7 @@ struct hwrm_fw_qstatus_input { 
	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT		   0x1UL

	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL	   0x2UL

	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE		   0x3UL

	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_RSVD		   0x4UL

	#define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST		   0x4UL

	u8 unused_0[7];

};
@@ -4572,6 +4808,16 @@ struct hwrm_fw_set_structured_data_output { 
	u8 valid;

};



/* Command specific Error Codes (8 bytes) */

struct hwrm_fw_set_structured_data_cmd_err {

	u8 code;

	#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN       0x0UL

	#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT   0x1UL

	#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT       0x2UL

	#define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID	   0x3UL

	u8 unused_0[7];

};



/* hwrm_fw_get_structured_data */

/* Input (32 bytes) */

struct hwrm_fw_get_structured_data_input {
@@ -4611,6 +4857,14 @@ struct hwrm_fw_get_structured_data_output { 
	u8 valid;

};



/* Command specific Error Codes (8 bytes) */

struct hwrm_fw_get_structured_data_cmd_err {

	u8 code;

	#define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN       0x0UL

	#define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID	   0x3UL

	u8 unused_0[7];

};



/* hwrm_exec_fwd_resp */

/* Input (128 bytes) */

struct hwrm_exec_fwd_resp_input {
@@ -5411,7 +5665,7 @@ struct cmd_nums { 
	#define HWRM_PORT_LPBK_CLR_STATS			   (0x26UL)

	#define HWRM_PORT_PHY_QCFG				   (0x27UL)

	#define HWRM_PORT_MAC_QCFG				   (0x28UL)

	#define RESERVED7					   (0x29UL)

	#define HWRM_PORT_MAC_PTP_QCFG				   (0x29UL)

	#define HWRM_PORT_PHY_QCAPS				   (0x2aUL)

	#define HWRM_PORT_PHY_I2C_WRITE			   (0x2bUL)

	#define HWRM_PORT_PHY_I2C_READ				   (0x2cUL)
@@ -5421,14 +5675,17 @@ struct cmd_nums { 
	#define HWRM_QUEUE_QPORTCFG				   (0x30UL)

	#define HWRM_QUEUE_QCFG				   (0x31UL)

	#define HWRM_QUEUE_CFG					   (0x32UL)

	#define RESERVED2					   (0x33UL)

	#define RESERVED3					   (0x34UL)

	#define HWRM_FUNC_VLAN_CFG				   (0x33UL)

	#define HWRM_FUNC_VLAN_QCFG				   (0x34UL)

	#define HWRM_QUEUE_PFCENABLE_QCFG			   (0x35UL)

	#define HWRM_QUEUE_PFCENABLE_CFG			   (0x36UL)

	#define HWRM_QUEUE_PRI2COS_QCFG			   (0x37UL)

	#define HWRM_QUEUE_PRI2COS_CFG				   (0x38UL)

	#define HWRM_QUEUE_COS2BW_QCFG				   (0x39UL)

	#define HWRM_QUEUE_COS2BW_CFG				   (0x3aUL)

	#define HWRM_QUEUE_DSCP_QCAPS				   (0x3bUL)

	#define HWRM_QUEUE_DSCP2PRI_QCFG			   (0x3cUL)

	#define HWRM_QUEUE_DSCP2PRI_CFG			   (0x3dUL)

	#define HWRM_VNIC_ALLOC				   (0x40UL)

	#define HWRM_VNIC_FREE					   (0x41UL)

	#define HWRM_VNIC_CFG					   (0x42UL)
@@ -5455,7 +5712,7 @@ struct cmd_nums { 
	#define HWRM_CFA_L2_FILTER_FREE			   (0x91UL)

	#define HWRM_CFA_L2_FILTER_CFG				   (0x92UL)

	#define HWRM_CFA_L2_SET_RX_MASK			   (0x93UL)

	#define RESERVED4					   (0x94UL)

	#define HWRM_CFA_VLAN_ANTISPOOF_CFG			   (0x94UL)

	#define HWRM_CFA_TUNNEL_FILTER_ALLOC			   (0x95UL)

	#define HWRM_CFA_TUNNEL_FILTER_FREE			   (0x96UL)

	#define HWRM_CFA_ENCAP_RECORD_ALLOC			   (0x97UL)
@@ -5494,6 +5751,8 @@ struct cmd_nums { 
	#define HWRM_CFA_METER_PROFILE_CFG			   (0xf7UL)

	#define HWRM_CFA_METER_INSTANCE_ALLOC			   (0xf8UL)

	#define HWRM_CFA_METER_INSTANCE_FREE			   (0xf9UL)

	#define HWRM_CFA_VFR_ALLOC				   (0xfdUL)

	#define HWRM_CFA_VFR_FREE				   (0xfeUL)

	#define HWRM_CFA_VF_PAIR_ALLOC				   (0x100UL)

	#define HWRM_CFA_VF_PAIR_FREE				   (0x101UL)

	#define HWRM_CFA_VF_PAIR_INFO				   (0x102UL)
@@ -5502,6 +5761,9 @@ struct cmd_nums { 
	#define HWRM_CFA_FLOW_FLUSH				   (0x105UL)

	#define HWRM_CFA_FLOW_STATS				   (0x106UL)

	#define HWRM_CFA_FLOW_INFO				   (0x107UL)

	#define HWRM_CFA_DECAP_FILTER_ALLOC			   (0x108UL)

	#define HWRM_CFA_DECAP_FILTER_FREE			   (0x109UL)

	#define HWRM_CFA_VLAN_ANTISPOOF_QCFG			   (0x10aUL)

	#define HWRM_SELFTEST_QLIST				   (0x200UL)

	#define HWRM_SELFTEST_EXEC				   (0x201UL)

	#define HWRM_SELFTEST_IRQ				   (0x202UL)
@@ -5510,6 +5772,8 @@ struct cmd_nums { 
	#define HWRM_DBG_WRITE_DIRECT				   (0xff12UL)

	#define HWRM_DBG_WRITE_INDIRECT			   (0xff13UL)

	#define HWRM_DBG_DUMP					   (0xff14UL)

	#define HWRM_DBG_ERASE_NVM				   (0xff15UL)

	#define HWRM_DBG_CFG					   (0xff16UL)

	#define HWRM_NVM_FACTORY_DEFAULTS			   (0xffeeUL)

	#define HWRM_NVM_VALIDATE_OPTION			   (0xffefUL)

	#define HWRM_NVM_FLUSH					   (0xfff0UL)

drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c

+6 −3
Original line number Diff line number Diff line
@@ -794,8 +794,10 @@ static int bnxt_vf_set_link(struct bnxt *bp, struct bnxt_vf_info *vf) 
					PORT_PHY_QCFG_RESP_LINK_LINK;

				phy_qcfg_resp.link_speed = cpu_to_le16(

					PORT_PHY_QCFG_RESP_LINK_SPEED_10GB);

				phy_qcfg_resp.duplex =

					PORT_PHY_QCFG_RESP_DUPLEX_FULL;

				phy_qcfg_resp.duplex_cfg =

					PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL;

				phy_qcfg_resp.duplex_state =

					PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL;

				phy_qcfg_resp.pause =

					(PORT_PHY_QCFG_RESP_PAUSE_TX |

					 PORT_PHY_QCFG_RESP_PAUSE_RX);
@@ -804,7 +806,8 @@ static int bnxt_vf_set_link(struct bnxt *bp, struct bnxt_vf_info *vf) 
			/* force link down */

			phy_qcfg_resp.link = PORT_PHY_QCFG_RESP_LINK_NO_LINK;

			phy_qcfg_resp.link_speed = 0;

			phy_qcfg_resp.duplex = PORT_PHY_QCFG_RESP_DUPLEX_HALF;

			phy_qcfg_resp.duplex_state =

				PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF;

			phy_qcfg_resp.pause = 0;

		}

		rc = bnxt_hwrm_fwd_resp(bp, vf, &phy_qcfg_resp,