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Commit ac88b6ec authored by Vivek Natarajan's avatar Vivek Natarajan Committed by John W. Linville
Browse files

ath9k: Add support for AR9287 based chipsets. 



Signed-off-by: default avatarVivek Natarajan <vnatarajan@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 3fa52056

drivers/net/wireless/ath/ath9k/calib.c

+14 −8
Original line number Diff line number Diff line
@@ -116,7 +116,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah, 
				"NF calibrated [ctl] [chain 1] is %d\n", nf);

		nfarray[1] = nf;



		if (!AR_SREV_9280(ah)) {

		if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {

			nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),

					AR_PHY_CH2_MINCCA_PWR);

			if (nf & 0x100)
@@ -154,7 +154,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah, 
				"NF calibrated [ext] [chain 1] is %d\n", nf);

		nfarray[4] = nf;



		if (!AR_SREV_9280(ah)) {

		if (!AR_SREV_9280(ah) && !AR_SREV_9287(ah)) {

			nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),

					AR_PHY_CH2_EXT_MINCCA_PWR);

			if (nf & 0x100)
@@ -613,7 +613,7 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan) 


	if (AR_SREV_9285(ah))

		chainmask = 0x9;

	else if (AR_SREV_9280(ah))

	else if (AR_SREV_9280(ah) || AR_SREV_9287(ah))

		chainmask = 0x1B;

	else

		chainmask = 0x3F;
@@ -873,7 +873,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, 
		if (AR_SREV_9285_11_OR_LATER(ah))

			ath9k_hw_9285_pa_cal(ah);



		if (OLC_FOR_AR9280_20_LATER)

		if (OLC_FOR_AR9280_20_LATER || OLC_FOR_AR9287_10_LATER)

			ath9k_olc_temp_compensation(ah);

		ath9k_hw_getnf(ah, chan);

		ath9k_hw_loadnf(ah, ah->curchan);
@@ -929,8 +929,11 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) 
			return false;

	} else {

		if (AR_SREV_9280_10_OR_LATER(ah)) {

			REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);

			REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);

			if (!AR_SREV_9287_10_OR_LATER(ah))

				REG_CLR_BIT(ah, AR_PHY_ADC_CTL,

					    AR_PHY_ADC_CTL_OFF_PWDADC);

			REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,

				    AR_PHY_AGC_CONTROL_FLTR_CAL);

		}



		/* Calibrate the AGC */
@@ -948,8 +951,11 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) 
		}



		if (AR_SREV_9280_10_OR_LATER(ah)) {

			REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);

			REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);

			if (!AR_SREV_9287_10_OR_LATER(ah))

				REG_SET_BIT(ah, AR_PHY_ADC_CTL,

					    AR_PHY_ADC_CTL_OFF_PWDADC);

			REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,

				    AR_PHY_AGC_CONTROL_FLTR_CAL);

		}

	}

drivers/net/wireless/ath/ath9k/eeprom.c

+1201 −2

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/wireless/ath/ath9k/eeprom.h

+162 −1
Original line number Diff line number Diff line
@@ -100,6 +100,8 @@ 
#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)

#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \

				 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))

#define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_10_OR_LATER(ah) && \

				 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))



#define AR_EEPROM_RFSILENT_GPIO_SEL     0x001c

#define AR_EEPROM_RFSILENT_GPIO_SEL_S   2
@@ -176,6 +178,57 @@ 


#define AR9280_TX_GAIN_TABLE_SIZE 22



#define AR9287_EEP_VER               0xE

#define AR9287_EEP_VER_MINOR_MASK    0xFFF

#define AR9287_EEP_MINOR_VER_1       0x1

#define AR9287_EEP_MINOR_VER_2       0x2

#define AR9287_EEP_MINOR_VER_3       0x3

#define AR9287_EEP_MINOR_VER         AR9287_EEP_MINOR_VER_3

#define AR9287_EEP_MINOR_VER_b       AR9287_EEP_MINOR_VER

#define AR9287_EEP_NO_BACK_VER       AR9287_EEP_MINOR_VER_1



#define AR9287_EEP_START_LOC            128

#define AR9287_NUM_2G_CAL_PIERS         3

#define AR9287_NUM_2G_CCK_TARGET_POWERS 3

#define AR9287_NUM_2G_20_TARGET_POWERS  3

#define AR9287_NUM_2G_40_TARGET_POWERS  3

#define AR9287_NUM_CTLS              	12

#define AR9287_NUM_BAND_EDGES        	4

#define AR9287_NUM_PD_GAINS             4

#define AR9287_PD_GAINS_IN_MASK         4

#define AR9287_PD_GAIN_ICEPTS           1

#define AR9287_EEPROM_MODAL_SPURS       5

#define AR9287_MAX_RATE_POWER           63

#define AR9287_NUM_PDADC_VALUES         128

#define AR9287_NUM_RATES                16

#define AR9287_BCHAN_UNUSED             0xFF

#define AR9287_MAX_PWR_RANGE_IN_HALF_DB 64

#define AR9287_OPFLAGS_11A              0x01

#define AR9287_OPFLAGS_11G              0x02

#define AR9287_OPFLAGS_2G_HT40          0x08

#define AR9287_OPFLAGS_2G_HT20          0x20

#define AR9287_OPFLAGS_5G_HT40          0x04

#define AR9287_OPFLAGS_5G_HT20          0x10

#define AR9287_EEPMISC_BIG_ENDIAN       0x01

#define AR9287_EEPMISC_WOW              0x02

#define AR9287_MAX_CHAINS               2

#define AR9287_ANT_16S                  32

#define AR9287_custdatasize             20



#define AR9287_NUM_ANT_CHAIN_FIELDS     6

#define AR9287_NUM_ANT_COMMON_FIELDS    4

#define AR9287_SIZE_ANT_CHAIN_FIELD     2

#define AR9287_SIZE_ANT_COMMON_FIELD    4

#define AR9287_ANT_CHAIN_MASK           0x3

#define AR9287_ANT_COMMON_MASK          0xf

#define AR9287_CHAIN_0_IDX              0

#define AR9287_CHAIN_1_IDX              1

#define AR9287_DATA_SZ                  32



#define AR9287_PWR_TABLE_OFFSET_DB  -5



#define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)



enum eeprom_param {

	EEP_NFTHRESH_5,

	EEP_NFTHRESH_2,
@@ -199,7 +252,11 @@ enum eeprom_param { 
	EEP_OL_PWRCTRL,

	EEP_RC_CHAIN_MASK,

	EEP_DAC_HPWR_5G,

	EEP_FRAC_N_5G

	EEP_FRAC_N_5G,

	EEP_DEV_TYPE,

	EEP_TEMPSENSE_SLOPE,

	EEP_TEMPSENSE_SLOPE_PAL_ON,

	EEP_PWR_TABLE_OFFSET

};



enum ar5416_rates {
@@ -368,6 +425,65 @@ struct modal_eep_4k_header { 
	struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];

} __packed;



struct base_eep_ar9287_header {

    u16  length;

    u16  checksum;

    u16  version;

    u8 opCapFlags;

    u8   eepMisc;

    u16  regDmn[2];

    u8   macAddr[6];

    u8   rxMask;

    u8   txMask;

    u16  rfSilent;

    u16  blueToothOptions;

    u16  deviceCap;

    u32  binBuildNumber;

    u8   deviceType;

    u8   openLoopPwrCntl;

    int8_t    pwrTableOffset;

    int8_t     tempSensSlope;

    int8_t     tempSensSlopePalOn;

    u8   futureBase[29];

} __packed;



struct modal_eep_ar9287_header {

    u32  antCtrlChain[AR9287_MAX_CHAINS];

    u32  antCtrlCommon;

    int8_t    antennaGainCh[AR9287_MAX_CHAINS];

    u8   switchSettling;

    u8   txRxAttenCh[AR9287_MAX_CHAINS];

    u8   rxTxMarginCh[AR9287_MAX_CHAINS];

    int8_t    adcDesiredSize;

    u8   txEndToXpaOff;

    u8   txEndToRxOn;

    u8   txFrameToXpaOn;

    u8   thresh62;

    int8_t    noiseFloorThreshCh[AR9287_MAX_CHAINS];

    u8   xpdGain;

    u8   xpd;

    int8_t    iqCalICh[AR9287_MAX_CHAINS];

    int8_t    iqCalQCh[AR9287_MAX_CHAINS];

    u8   pdGainOverlap;

    u8   xpaBiasLvl;

    u8   txFrameToDataStart;

    u8   txFrameToPaOn;

    u8   ht40PowerIncForPdadc;

    u8   bswAtten[AR9287_MAX_CHAINS];

    u8   bswMargin[AR9287_MAX_CHAINS];

    u8   swSettleHt40;

	u8   version;

    u8   db1;

    u8   db2;

    u8   ob_cck;

    u8   ob_psk;

    u8   ob_qam;

    u8   ob_pal_off;

    u8   futureModal[30];

    struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS];

} __packed;







struct cal_data_per_freq {

	u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
@@ -402,6 +518,29 @@ struct cal_ctl_edges { 
} __packed;

#endif



struct cal_data_op_loop_ar9287 {

	u8 pwrPdg[2][5];

	u8 vpdPdg[2][5];

	u8 pcdac[2][5];

	u8 empty[2][5];

} __packed;





struct cal_data_per_freq_ar9287 {

	u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];

	u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];

} __packed;



union cal_data_per_freq_ar9287_u {

	struct cal_data_op_loop_ar9287 calDataOpen;

	struct cal_data_per_freq_ar9287 calDataClose;

} __packed;



struct cal_ctl_data_ar9287 {

	struct cal_ctl_edges

	ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES];

} __packed;



struct cal_ctl_data {

	struct cal_ctl_edges

	ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
@@ -461,6 +600,27 @@ struct ar5416_eeprom_4k { 
	u8 padding;

} __packed;



struct ar9287_eeprom_t {

	struct base_eep_ar9287_header  baseEepHeader;

	u8 custData[AR9287_DATA_SZ];

	struct modal_eep_ar9287_header modalHeader;

	u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];

	union cal_data_per_freq_ar9287_u

	 calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS];

	struct cal_target_power_leg

	 calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS];

	struct cal_target_power_leg

	 calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS];

	struct cal_target_power_ht

	 calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS];

	struct cal_target_power_ht

	 calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS];

	u8 ctlIndex[AR9287_NUM_CTLS];

	struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS];

	u8 padding;

} __packed;





enum reg_ext_bitmap {

	REG_EXT_JAPAN_MIDBAND = 1,

	REG_EXT_FCC_DFS_HT40 = 2,
@@ -480,6 +640,7 @@ struct ath9k_country_entry { 
enum ath9k_eep_map {

	EEP_MAP_DEFAULT = 0x0,

	EEP_MAP_4KBITS,

	EEP_MAP_AR9287,

	EEP_MAP_MAX

};

drivers/net/wireless/ath/ath9k/hw.c

+96 −14
Original line number Diff line number Diff line
@@ -380,6 +380,9 @@ static const char *ath9k_hw_devname(u16 devid) 
		return "Atheros 9280";

	case AR9285_DEVID_PCIE:

		return "Atheros 9285";

	case AR5416_DEVID_AR9287_PCI:

	case AR5416_DEVID_AR9287_PCIE:

		return "Atheros 9287";

	}



	return NULL;
@@ -660,7 +663,8 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, 
	if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&

	    (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&

	    (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&

	    (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {

	    (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) &&

	    (!AR_SREV_9285(ah)) && (!AR_SREV_9287(ah))) {

		DPRINTF(sc, ATH_DBG_FATAL,

			"Mac Chip Rev 0x%02x.%x is not supported by "

			"this driver\n", ah->hw_version.macVersion,
@@ -700,8 +704,37 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, 
	ah->ani_function = ATH9K_ANI_ALL;

	if (AR_SREV_9280_10_OR_LATER(ah))

		ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;

	if (AR_SREV_9287_11_OR_LATER(ah)) {

		INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,

				ARRAY_SIZE(ar9287Modes_9287_1_1), 6);

		INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,

				ARRAY_SIZE(ar9287Common_9287_1_1), 2);

		if (ah->config.pcie_clock_req)

			INIT_INI_ARRAY(&ah->iniPcieSerdes,

			ar9287PciePhy_clkreq_off_L1_9287_1_1,

			ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);

		else

			INIT_INI_ARRAY(&ah->iniPcieSerdes,

			ar9287PciePhy_clkreq_always_on_L1_9287_1_1,

			ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),

					2);

	} else if (AR_SREV_9287_10_OR_LATER(ah)) {

		INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,

				ARRAY_SIZE(ar9287Modes_9287_1_0), 6);

		INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,

				ARRAY_SIZE(ar9287Common_9287_1_0), 2);



		if (ah->config.pcie_clock_req)

			INIT_INI_ARRAY(&ah->iniPcieSerdes,

			ar9287PciePhy_clkreq_off_L1_9287_1_0,

			ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);

		else

			INIT_INI_ARRAY(&ah->iniPcieSerdes,

			ar9287PciePhy_clkreq_always_on_L1_9287_1_0,

			ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),

				  2);

	} else if (AR_SREV_9285_12_OR_LATER(ah)) {



	if (AR_SREV_9285_12_OR_LATER(ah)) {



		INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,

			       ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
@@ -842,7 +875,28 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, 
	if (ecode != 0)

		goto bad;



	if (AR_SREV_9285_12_OR_LATER(ah)) {

	if (AR_SREV_9287_11(ah))

		INIT_INI_ARRAY(&ah->iniModesRxGain,

		ar9287Modes_rx_gain_9287_1_1,

		ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);

	else if (AR_SREV_9287_10(ah))

		INIT_INI_ARRAY(&ah->iniModesRxGain,

		ar9287Modes_rx_gain_9287_1_0,

		ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);

	else if (AR_SREV_9280_20(ah))

		ath9k_hw_init_rxgain_ini(ah);



	if (AR_SREV_9287_11(ah)) {

		INIT_INI_ARRAY(&ah->iniModesTxGain,

		ar9287Modes_tx_gain_9287_1_1,

		ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);

	} else if (AR_SREV_9287_10(ah)) {

		INIT_INI_ARRAY(&ah->iniModesTxGain,

		ar9287Modes_tx_gain_9287_1_0,

		ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);

	} else if (AR_SREV_9280_20(ah)) {

		ath9k_hw_init_txgain_ini(ah);

	} else if (AR_SREV_9285_12_OR_LATER(ah)) {

		u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);



		/* txgain table */
@@ -858,14 +912,6 @@ static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, 


	}



	/* rxgain table */

	if (AR_SREV_9280_20(ah))

		ath9k_hw_init_rxgain_ini(ah);



	/* txgain table */

	if (AR_SREV_9280_20(ah))

		ath9k_hw_init_txgain_ini(ah);



	ath9k_hw_fill_cap_info(ah);



	if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
@@ -1165,6 +1211,8 @@ struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error) 
	case AR9280_DEVID_PCI:

	case AR9280_DEVID_PCIE:

	case AR9285_DEVID_PCIE:

	case AR5416_DEVID_AR9287_PCI:

	case AR5416_DEVID_AR9287_PCIE:

		ah = ath9k_hw_do_attach(devid, sc, error);

		break;

	default:
@@ -1341,10 +1389,11 @@ static int ath9k_hw_process_ini(struct ath_hw *ah, 
		DO_DELAY(regWrites);

	}



	if (AR_SREV_9280(ah))

	if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))

		REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);



	if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah))

	if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||

	    AR_SREV_9287_10_OR_LATER(ah))

		REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);



	for (i = 0; i < ah->iniCommon.ia_rows; i++) {
@@ -2254,6 +2303,16 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 
	if (AR_SREV_9280_10_OR_LATER(ah))

		REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);



	if (AR_SREV_9287_10_OR_LATER(ah)) {

		/* Enable ASYNC FIFO */

		REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,

				AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);

		REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);

		REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,

				AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);

		REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,

				AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);

	}

	r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);

	if (r)

		return r;
@@ -2330,6 +2389,27 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 


	ath9k_hw_init_user_settings(ah);



	if (AR_SREV_9287_10_OR_LATER(ah)) {

		REG_WRITE(ah, AR_D_GBL_IFS_SIFS,

			  AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);

		REG_WRITE(ah, AR_D_GBL_IFS_SLOT,

			  AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);

		REG_WRITE(ah, AR_D_GBL_IFS_EIFS,

			  AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);



		REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);

		REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);



		REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,

			    AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);

		REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,

			      AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);

	}

	if (AR_SREV_9287_10_OR_LATER(ah)) {

		REG_SET_BIT(ah, AR_PCU_MISC_MODE2,

				AR_PCU_MISC_MODE2_ENABLE_AGGWEP);

	}



	REG_WRITE(ah, AR_STA_ID1,

		  REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
@@ -3644,7 +3724,9 @@ u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) 
	if (gpio >= ah->caps.num_gpio_pins)

		return 0xffffffff;



	if (AR_SREV_9285_10_OR_LATER(ah))

	if (AR_SREV_9287_10_OR_LATER(ah))

		return MS_REG_READ(AR9287, gpio) != 0;

	else if (AR_SREV_9285_10_OR_LATER(ah))

		return MS_REG_READ(AR9285, gpio) != 0;

	else if (AR_SREV_9280_10_OR_LATER(ah))

		return MS_REG_READ(AR928X, gpio) != 0;

drivers/net/wireless/ath/ath9k/hw.h

+4 −0
Original line number Diff line number Diff line
@@ -42,6 +42,9 @@ 
#define AR_SUBVENDOR_ID_NEW_A	0x7065

#define AR5416_MAGIC		0x19641014



#define AR5416_DEVID_AR9287_PCI  0x002D

#define AR5416_DEVID_AR9287_PCIE 0x002E



/* Register read/write primitives */

#define REG_WRITE(_ah, _reg, _val) ath9k_iowrite32((_ah), (_reg), (_val))

#define REG_READ(_ah, _reg) ath9k_ioread32((_ah), (_reg))
@@ -400,6 +403,7 @@ struct ath_hw { 
	union {

		struct ar5416_eeprom_def def;

		struct ar5416_eeprom_4k map4k;

		struct ar9287_eeprom_t map9287;

	} eeprom;

	const struct eeprom_ops *eep_ops;

	enum ath9k_eep_map eep_map;