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Commit ac05474e authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "clk: qcom: khaje: Update freq_tbl and pll configurations"

parents b81647a0 8cd16017

drivers/clk/qcom/debugcc-khaje.c

+2 −2
Original line number Diff line number Diff line
@@ -40,8 +40,8 @@ static int apss_cc_debug_mux_pre_divs[] = { 


static struct clk_debug_mux apss_cc_debug_mux = {

	.priv = &debug_mux_priv,

	.debug_offset = 0x1C,

	.post_div_offset = 0x1C,

	.debug_offset = 0x0,

	.post_div_offset = 0x0,

	.cbcr_offset = U32_MAX,

	.src_sel_mask = 0x3FF00,

	.src_sel_shift = 8,

drivers/clk/qcom/gcc-khaje.c

+2 −9
Original line number Diff line number Diff line
@@ -671,8 +671,8 @@ static const struct alpha_pll_config gpll9_config = { 
	.l = 0x4B,

	.alpha = 0x0,

	.config_ctl_val = 0x08200800,

	.config_ctl_hi_val = 0x05022001,

	.config_ctl_hi1_val = 0x00000010,

	.config_ctl_hi_val = 0x05022011,

	.config_ctl_hi1_val = 0x08000000,

	.user_ctl_val = 0x00000301,

};
@@ -1229,13 +1229,6 @@ static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { 
	},

};



static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),

	F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),

	{ }

};



static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {

	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),

	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),

drivers/clk/qcom/gpucc-khaje.c

+3 −1
Original line number Diff line number Diff line
@@ -88,7 +88,7 @@ static const struct alpha_pll_config gpu_cc_pll0_config = { 
	.config_ctl_val = 0x08200800,

	.config_ctl_hi_val = 0x05022001,

	.config_ctl_hi1_val = 0x00000010,

	.user_ctl_val = 0x00000101,

	.user_ctl_val = 0x01000101,

};



static struct clk_alpha_pll gpu_cc_pll0 = {
@@ -202,7 +202,9 @@ static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { 
	F(600000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),

	F(785000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),

	F(820000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),

	F(980000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),

	F(1025000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),

	F(1100000000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),

	F(1114800000, P_GPU_CC_PLL0_OUT_MAIN, 1, 0, 0),

	{ }

};