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Commit ab6bad05 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: Update CKS on/ CKS off voltage offset calculation. 



As get the right evv voltage, update them to latest coefficients to
align with BB.

agd: squash in Slava's 32 bit build fix

Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e5eb3717

drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

+10 −13
Original line number Diff line number Diff line
@@ -98,7 +98,6 @@ 
#define PCIE_BUS_CLK                10000

#define TCLK                        (PCIE_BUS_CLK / 10)



#define CEILING_UCHAR(double) ((double-(uint8_t)(double)) > 0 ? (uint8_t)(double+1) : (uint8_t)(double))



static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =

{ {600, 1050, 3, 0}, {600, 1050, 6, 1} };
@@ -1807,27 +1806,25 @@ static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) 


	ro = efuse * (max -min)/255 + min;



	/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset

	 * there is a little difference in calculating

	 * volt_with_cks with windows */

	/* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */

	for (i = 0; i < sclk_table->count; i++) {

		data->smc_state_table.Sclk_CKS_masterEn0_7 |=

				sclk_table->entries[i].cks_enable << i;

		if (hwmgr->chip_id == CHIP_POLARIS10) {

			volt_without_cks = (uint32_t)((2753594000 + (sclk_table->entries[i].clk/100) * 136418 -(ro - 70) * 1000000) / \

			volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 -(ro - 70) * 1000000) / \

						(2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));

			volt_with_cks = (uint32_t)((279720200 + sclk_table->entries[i].clk * 3232 - (ro - 65) * 100000000) / \

					(252248000 - sclk_table->entries[i].clk/100 * 115764));

			volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \

					(2522480 - sclk_table->entries[i].clk/100 * 115764/100));

		} else {

			volt_without_cks = (uint32_t)((2416794800 + (sclk_table->entries[i].clk/100) * 1476925/10 -(ro - 50) * 1000000) / \

						(2625416 - (sclk_table->entries[i].clk/100) * 12586807/10000));

			volt_with_cks = (uint32_t)((2999656000 + sclk_table->entries[i].clk * 392803/100 - (ro - 44) * 1000000) / \

					(3422454 - sclk_table->entries[i].clk/100 * 18886376/10000));

			volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 -(ro - 50) * 1000000) / \

						(2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));

			volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \

					(3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));

		}



		if (volt_without_cks >= volt_with_cks)

			volt_offset = (uint8_t)CEILING_UCHAR((volt_without_cks - volt_with_cks +

					sclk_table->entries[i].cks_voffset) * 100 / 625);

			volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +

					sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);



		data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;

	}