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Commit ab690d9f authored by Joe Perches's avatar Joe Perches Committed by Adrian Bunk
Browse files

include/asm-m68knommu/: Spelling fixes 



Signed-off-by: default avatarJoe Perches <joe@perches.com>
Acked-by: default avatarGreg Ungerer <gerg@uclinux.org>
Signed-off-by: default avatarAdrian Bunk <bunk@kernel.org>
parent 62018b5b

include/asm-m68knommu/bitops.h

+1 −1
Original line number Diff line number Diff line
@@ -262,7 +262,7 @@ static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned lon 
		 * tmp = __swab32(*(p++));

		 * tmp |= ~0UL >> (32-offset);

		 *

		 * but this would decrease preformance, so we change the

		 * but this would decrease performance, so we change the

		 * shift:

		 */

		tmp = *(p++);

include/asm-m68knommu/commproc.h

+1 −1
Original line number Diff line number Diff line
@@ -715,7 +715,7 @@ extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id); 
#define	CICR_SCC_SCC3		((uint)0x00200000)	/* SCC3 @ SCCc */

#define	CICR_SCB_SCC2		((uint)0x00040000)	/* SCC2 @ SCCb */

#define	CICR_SCA_SCC1		((uint)0x00000000)	/* SCC1 @ SCCa */

#define CICR_IRL_MASK		((uint)0x0000e000)	/* Core interrrupt */

#define CICR_IRL_MASK		((uint)0x0000e000)	/* Core interrupt */

#define CICR_HP_MASK		((uint)0x00001f00)	/* Hi-pri int. */

#define CICR_IEN		((uint)0x00000080)	/* Int. enable */

#define CICR_SPS		((uint)0x00000001)	/* SCC Spread */

include/asm-m68knommu/delay.h

+1 −1
Original line number Diff line number Diff line
@@ -68,7 +68,7 @@ static inline void _udelay(unsigned long usecs) 
/*

 *	Moved the udelay() function into library code, no longer inlined.

 *	I had to change the algorithm because we are overflowing now on

 *	the faster ColdFire parts. The code is a little biger, so it makes

 *	the faster ColdFire parts. The code is a little bigger, so it makes

 *	sense to library it.

 */

extern void udelay(unsigned long usecs);

include/asm-m68knommu/m5249sim.h

+2 −2
Original line number Diff line number Diff line
@@ -43,10 +43,10 @@ 
#define MCFSIM_CSAR1		0x8c		/* CS 1 Address reg (r/w) */

#define MCFSIM_CSMR1		0x90		/* CS 1 Mask reg (r/w) */

#define MCFSIM_CSCR1		0x96		/* CS 1 Control reg (r/w) */

#define MCFSIM_CSAR2		0x98		/* CS 2 Adress reg (r/w) */

#define MCFSIM_CSAR2		0x98		/* CS 2 Address reg (r/w) */

#define MCFSIM_CSMR2		0x9c		/* CS 2 Mask reg (r/w) */

#define MCFSIM_CSCR2		0xa2		/* CS 2 Control reg (r/w) */

#define MCFSIM_CSAR3		0xa4		/* CS 3 Adress reg (r/w) */

#define MCFSIM_CSAR3		0xa4		/* CS 3 Address reg (r/w) */

#define MCFSIM_CSMR3		0xa8		/* CS 3 Mask reg (r/w) */

#define MCFSIM_CSCR3		0xae		/* CS 3 Control reg (r/w) */

include/asm-m68knommu/m5307sim.h

+6 −6
Original line number Diff line number Diff line
@@ -64,22 +64,22 @@ 
#define MCFSIM_CSMR7		0xda		/* CS 7 Mask reg (r/w) */

#define MCFSIM_CSCR7		0xde		/* CS 7 Control reg (r/w) */

#else

#define MCFSIM_CSAR2		0x98		/* CS 2 Adress reg (r/w) */

#define MCFSIM_CSAR2		0x98		/* CS 2 Address reg (r/w) */

#define MCFSIM_CSMR2		0x9c		/* CS 2 Mask reg (r/w) */

#define MCFSIM_CSCR2		0xa2		/* CS 2 Control reg (r/w) */

#define MCFSIM_CSAR3		0xa4		/* CS 3 Adress reg (r/w) */

#define MCFSIM_CSAR3		0xa4		/* CS 3 Address reg (r/w) */

#define MCFSIM_CSMR3		0xa8		/* CS 3 Mask reg (r/w) */

#define MCFSIM_CSCR3		0xae		/* CS 3 Control reg (r/w) */

#define MCFSIM_CSAR4		0xb0		/* CS 4 Adress reg (r/w) */

#define MCFSIM_CSAR4		0xb0		/* CS 4 Address reg (r/w) */

#define MCFSIM_CSMR4		0xb4		/* CS 4 Mask reg (r/w) */

#define MCFSIM_CSCR4		0xba		/* CS 4 Control reg (r/w) */

#define MCFSIM_CSAR5		0xbc		/* CS 5 Adress reg (r/w) */

#define MCFSIM_CSAR5		0xbc		/* CS 5 Address reg (r/w) */

#define MCFSIM_CSMR5		0xc0		/* CS 5 Mask reg (r/w) */

#define MCFSIM_CSCR5		0xc6		/* CS 5 Control reg (r/w) */

#define MCFSIM_CSAR6		0xc8		/* CS 6 Adress reg (r/w) */

#define MCFSIM_CSAR6		0xc8		/* CS 6 Address reg (r/w) */

#define MCFSIM_CSMR6		0xcc		/* CS 6 Mask reg (r/w) */

#define MCFSIM_CSCR6		0xd2		/* CS 6 Control reg (r/w) */

#define MCFSIM_CSAR7		0xd4		/* CS 7 Adress reg (r/w) */

#define MCFSIM_CSAR7		0xd4		/* CS 7 Address reg (r/w) */

#define MCFSIM_CSMR7		0xd8		/* CS 7 Mask reg (r/w) */

#define MCFSIM_CSCR7		0xde		/* CS 7 Control reg (r/w) */

#endif /* CONFIG_OLDMASK */