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Commit ab5f9eba authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "This contains fixes for exynos, amdgpu, radeon, i915 and qxl.

  It also contains some fixes to the core drm edid parser.

  qxl:
   - fix for a cursor hotspot issue

  radeon:
   - some MST fixes that I've been running locally and make my monitor a
     bit happier

  exynos:
   - fix some regressions and build fixes

  amdgpu:
   - a couple of small fixes

  i915:
   - two DP MST fixes and a couple of other regression fixes

  Nothing too out of the ordinary or surprising at this point"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  drm/exynos: Use VIDEO_SAMSUNG_S5P_G2D=n as G2D Kconfig dependency
  drm/exynos: fix a warning message
  drm/exynos: mic: fix an error code
  drm/exynos: fimd: fix broken dp_clock control
  drm/exynos: build fbdev code conditionally
  drm/exynos: fix adjusted_mode pointer in exynos_plane_mode_set
  drm/exynos: fix error handling in exynos_drm_subdrv_open
  drm/amd/amdgpu: fix irq domain remove for tonga ih
  drm/i915: fix deadlock on lid open
  drm/radeon: use helper for mst connector dpms.
  drm/radeon/mst: port some MST setup code from DAL.
  drm/amdgpu: add invisible pin size statistic
  drm/edid: Fix DMT 1024x768@43Hz (interlaced) timings
  drm/i915: Exit cherryview_irq_handler() after one pass
  drm/i915: Call intel_dp_mst_resume() before resuming displays
  drm/i915: Fix race condition in intel_dp_destroy_mst_connector()
  drm/edid: Fix parsing of EDID 1.4 Established Timings III descriptor
  drm/edid: Fix EDID Established Timings I and II
  drm/qxl: fix cursor position with non-zero hotspot
parents 60ea7bb0 ff3e84e8

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+1 −0
Original line number Diff line number Diff line
@@ -2034,6 +2034,7 @@ struct amdgpu_device { 


	/* tracking pinned memory */

	u64 vram_pin_size;

	u64 invisible_pin_size;

	u64 gart_pin_size;



	/* amdkfd interface */

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+1 −1
Original line number Diff line number Diff line
@@ -384,7 +384,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file 
		vram_gtt.vram_size = adev->mc.real_vram_size;

		vram_gtt.vram_size -= adev->vram_pin_size;

		vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;

		vram_gtt.vram_cpu_accessible_size -= adev->vram_pin_size;

		vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size);

		vram_gtt.gtt_size  = adev->mc.gtt_size;

		vram_gtt.gtt_size -= adev->gart_pin_size;

		return copy_to_user(out, &vram_gtt,

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

+8 −4
Original line number Diff line number Diff line
@@ -424,9 +424,11 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 
		bo->pin_count = 1;

		if (gpu_addr != NULL)

			*gpu_addr = amdgpu_bo_gpu_offset(bo);

		if (domain == AMDGPU_GEM_DOMAIN_VRAM)

		if (domain == AMDGPU_GEM_DOMAIN_VRAM) {

			bo->adev->vram_pin_size += amdgpu_bo_size(bo);

		else

			if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)

				bo->adev->invisible_pin_size += amdgpu_bo_size(bo);

		} else

			bo->adev->gart_pin_size += amdgpu_bo_size(bo);

	} else {

		dev_err(bo->adev->dev, "%p pin failed\n", bo);
@@ -456,9 +458,11 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo) 
	}

	r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);

	if (likely(r == 0)) {

		if (bo->tbo.mem.mem_type == TTM_PL_VRAM)

		if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {

			bo->adev->vram_pin_size -= amdgpu_bo_size(bo);

		else

			if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)

				bo->adev->invisible_pin_size -= amdgpu_bo_size(bo);

		} else

			bo->adev->gart_pin_size -= amdgpu_bo_size(bo);

	} else {

		dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

+1 −1
Original line number Diff line number Diff line
@@ -307,7 +307,7 @@ static int tonga_ih_sw_fini(void *handle) 


	amdgpu_irq_fini(adev);

	amdgpu_ih_ring_fini(adev);

	amdgpu_irq_add_domain(adev);

	amdgpu_irq_remove_domain(adev);



	return 0;

}

drivers/gpu/drm/drm_edid.c

+5 −5
Original line number Diff line number Diff line
@@ -205,7 +205,7 @@ static const struct drm_display_mode drm_dmt_modes[] = { 
		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },

	/* 0x0f - 1024x768@43Hz, interlace */

	{ DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,

		   1208, 1264, 0, 768, 768, 772, 817, 0,

		   1208, 1264, 0, 768, 768, 776, 817, 0,

		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |

		   DRM_MODE_FLAG_INTERLACE) },

	/* 0x10 - 1024x768@60Hz */
@@ -522,12 +522,12 @@ static const struct drm_display_mode edid_est_modes[] = { 
		   720, 840, 0, 480, 481, 484, 500, 0,

		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */

	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,

		   704,  832, 0, 480, 489, 491, 520, 0,

		   704,  832, 0, 480, 489, 492, 520, 0,

		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */

	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,

		   768,  864, 0, 480, 483, 486, 525, 0,

		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */

	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,

	{ DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,

		   752, 800, 0, 480, 490, 492, 525, 0,

		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */

	{ DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
@@ -539,7 +539,7 @@ static const struct drm_display_mode edid_est_modes[] = { 
	{ DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,

		   1440, 1688, 0, 1024, 1025, 1028, 1066, 0,

		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */

	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,

	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,

		   1136, 1312, 0,  768, 769, 772, 800, 0,

		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */

	{ DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
@@ -2241,7 +2241,7 @@ drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 
{

	int i, j, m, modes = 0;

	struct drm_display_mode *mode;

	u8 *est = ((u8 *)timing) + 5;

	u8 *est = ((u8 *)timing) + 6;



	for (i = 0; i < 6; i++) {

		for (j = 7; j >= 0; j--) {