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Commit aad82aa0 authored by Sujeev Dias's avatar Sujeev Dias Committed by Gerrit - the friendly Code Review server
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mhi: core: get bhie offset from devicetree node 



Some MHI based controllers do not have a BHIE offset defined in
mmio register space. For these controllers get the offset from
devicetree node.

CRs-Fixed: 2464900
Change-Id: Ib10d38aff366a56ac401dba5aac0b820411ad27d
Signed-off-by: default avatarSujeev Dias <sdias@codeaurora.org>
parent d4275441

drivers/bus/mhi/core/mhi_init.c

+16 −8
Original line number Original line Diff line number Diff line
@@ -1149,6 +1149,7 @@ static int of_parse_dt(struct mhi_controller *mhi_cntrl, 
	int ret;

	int ret;

	enum mhi_ee i;

	enum mhi_ee i;

	u32 *ee;

	u32 *ee;

	u32 bhie_offset;





	/* parse MHI channel configuration */

	/* parse MHI channel configuration */

	ret = of_parse_ch_cfg(mhi_cntrl, of_node);

	ret = of_parse_ch_cfg(mhi_cntrl, of_node);
@@ -1189,6 +1190,10 @@ static int of_parse_dt(struct mhi_controller *mhi_cntrl, 
		of_property_read_u32_index(of_node, "mhi,ee", ret, ee);

		of_property_read_u32_index(of_node, "mhi,ee", ret, ee);

	}

	}





	ret = of_property_read_u32(of_node, "mhi,bhie-offset", &bhie_offset);

	if (!ret)

		mhi_cntrl->bhie = mhi_cntrl->regs + bhie_offset;



	return 0;

	return 0;





error_ev_cfg:

error_ev_cfg:
@@ -1403,6 +1408,7 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl) 
		 * This controller supports rddm, we need to manually clear

		 * This controller supports rddm, we need to manually clear

		 * BHIE RX registers since por values are undefined.

		 * BHIE RX registers since por values are undefined.

		 */

		 */

		if (!mhi_cntrl->bhie) {

			ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF,

			ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF,

					   &bhie_off);

					   &bhie_off);

			if (ret) {

			if (ret) {
@@ -1410,9 +1416,11 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl) 
				goto bhie_error;

				goto bhie_error;

			}

			}





		memset_io(mhi_cntrl->regs + bhie_off + BHIE_RXVECADDR_LOW_OFFS,

			mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off;

			  0, BHIE_RXVECSTATUS_OFFS - BHIE_RXVECADDR_LOW_OFFS +

		}

			  4);



		memset_io(mhi_cntrl->bhie + BHIE_RXVECADDR_LOW_OFFS, 0,

			  BHIE_RXVECSTATUS_OFFS - BHIE_RXVECADDR_LOW_OFFS + 4);

	}

	}





	mhi_cntrl->pre_init = true;

	mhi_cntrl->pre_init = true;

drivers/bus/mhi/core/mhi_pm.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -812,8 +812,8 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl) 




	mhi_cntrl->bhi = mhi_cntrl->regs + val;

	mhi_cntrl->bhi = mhi_cntrl->regs + val;





	/* setup bhie offset */

	/* setup bhie offset if not set */

	if (mhi_cntrl->fbc_download) {

	if (mhi_cntrl->fbc_download && !mhi_cntrl->bhie) {

		ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF, &val);

		ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF, &val);

		if (ret) {

		if (ret) {

			write_unlock_irq(&mhi_cntrl->pm_lock);

			write_unlock_irq(&mhi_cntrl->pm_lock);