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Commit aab547ce authored by Michael Buesch's avatar Michael Buesch Committed by John W. Linville
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ssb: Add Gigabit Ethernet driver 



This adds the Gigabit Ethernet driver for the SSB
Gigabit Ethernet core. This driver actually is a frontend to
the Tigon3 driver. So the real work is done by tg3.
This device is used in the Linksys WRT350N.

Signed-off-by: default avatarMichael Buesch <mb@bu3sch.de>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 69d3b6f4

drivers/ssb/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -125,4 +125,13 @@ config SSB_DRIVER_EXTIF 


	  If unsure, say N



config SSB_DRIVER_GIGE

	bool "SSB Broadcom Gigabit Ethernet driver"

	depends on SSB_PCIHOST_POSSIBLE && SSB_EMBEDDED && MIPS

	help

	  Driver for the Sonics Silicon Backplane attached

	  Broadcom Gigabit Ethernet.



	  If unsure, say N



endmenu

drivers/ssb/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ ssb-y += driver_chipcommon.o 
ssb-$(CONFIG_SSB_DRIVER_MIPS)		+= driver_mipscore.o

ssb-$(CONFIG_SSB_DRIVER_EXTIF)		+= driver_extif.o

ssb-$(CONFIG_SSB_DRIVER_PCICORE)	+= driver_pcicore.o

ssb-$(CONFIG_SSB_DRIVER_GIGE)		+= driver_gige.o



# b43 pci-ssb-bridge driver

# Not strictly a part of SSB, but kept here for convenience

drivers/ssb/driver_gige.c

0 → 100644
+294 −0
Original line number Diff line number Diff line 
/*

 * Sonics Silicon Backplane

 * Broadcom Gigabit Ethernet core driver

 *

 * Copyright 2008, Broadcom Corporation

 * Copyright 2008, Michael Buesch <mb@bu3sch.de>

 *

 * Licensed under the GNU/GPL. See COPYING for details.

 */



#include <linux/ssb/ssb.h>

#include <linux/ssb/ssb_driver_gige.h>

#include <linux/pci.h>

#include <linux/pci_regs.h>





/*

MODULE_DESCRIPTION("SSB Broadcom Gigabit Ethernet driver");

MODULE_AUTHOR("Michael Buesch");

MODULE_LICENSE("GPL");

*/



static const struct ssb_device_id ssb_gige_tbl[] = {

	SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET_GBIT, SSB_ANY_REV),

	SSB_DEVTABLE_END

};

/* MODULE_DEVICE_TABLE(ssb, ssb_gige_tbl); */





static inline u8 gige_read8(struct ssb_gige *dev, u16 offset)

{

	return ssb_read8(dev->dev, offset);

}



static inline u16 gige_read16(struct ssb_gige *dev, u16 offset)

{

	return ssb_read16(dev->dev, offset);

}



static inline u32 gige_read32(struct ssb_gige *dev, u16 offset)

{

	return ssb_read32(dev->dev, offset);

}



static inline void gige_write8(struct ssb_gige *dev,

			       u16 offset, u8 value)

{

	ssb_write8(dev->dev, offset, value);

}



static inline void gige_write16(struct ssb_gige *dev,

				u16 offset, u16 value)

{

	ssb_write16(dev->dev, offset, value);

}



static inline void gige_write32(struct ssb_gige *dev,

				u16 offset, u32 value)

{

	ssb_write32(dev->dev, offset, value);

}



static inline

u8 gige_pcicfg_read8(struct ssb_gige *dev, unsigned int offset)

{

	BUG_ON(offset >= 256);

	return gige_read8(dev, SSB_GIGE_PCICFG + offset);

}



static inline

u16 gige_pcicfg_read16(struct ssb_gige *dev, unsigned int offset)

{

	BUG_ON(offset >= 256);

	return gige_read16(dev, SSB_GIGE_PCICFG + offset);

}



static inline

u32 gige_pcicfg_read32(struct ssb_gige *dev, unsigned int offset)

{

	BUG_ON(offset >= 256);

	return gige_read32(dev, SSB_GIGE_PCICFG + offset);

}



static inline

void gige_pcicfg_write8(struct ssb_gige *dev,

			unsigned int offset, u8 value)

{

	BUG_ON(offset >= 256);

	gige_write8(dev, SSB_GIGE_PCICFG + offset, value);

}



static inline

void gige_pcicfg_write16(struct ssb_gige *dev,

			 unsigned int offset, u16 value)

{

	BUG_ON(offset >= 256);

	gige_write16(dev, SSB_GIGE_PCICFG + offset, value);

}



static inline

void gige_pcicfg_write32(struct ssb_gige *dev,

			 unsigned int offset, u32 value)

{

	BUG_ON(offset >= 256);

	gige_write32(dev, SSB_GIGE_PCICFG + offset, value);

}



static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,

				    int reg, int size, u32 *val)

{

	struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);

	unsigned long flags;



	if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))

		return PCIBIOS_DEVICE_NOT_FOUND;

	if (reg >= 256)

		return PCIBIOS_DEVICE_NOT_FOUND;



	spin_lock_irqsave(&dev->lock, flags);

	switch (size) {

	case 1:

		*val = gige_pcicfg_read8(dev, reg);

		break;

	case 2:

		*val = gige_pcicfg_read16(dev, reg);

		break;

	case 4:

		*val = gige_pcicfg_read32(dev, reg);

		break;

	default:

		WARN_ON(1);

	}

	spin_unlock_irqrestore(&dev->lock, flags);



	return PCIBIOS_SUCCESSFUL;

}



static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,

				     int reg, int size, u32 val)

{

	struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);

	unsigned long flags;



	if ((PCI_SLOT(devfn) > 0) || (PCI_FUNC(devfn) > 0))

		return PCIBIOS_DEVICE_NOT_FOUND;

	if (reg >= 256)

		return PCIBIOS_DEVICE_NOT_FOUND;



	spin_lock_irqsave(&dev->lock, flags);

	switch (size) {

	case 1:

		gige_pcicfg_write8(dev, reg, val);

		break;

	case 2:

		gige_pcicfg_write16(dev, reg, val);

		break;

	case 4:

		gige_pcicfg_write32(dev, reg, val);

		break;

	default:

		WARN_ON(1);

	}

	spin_unlock_irqrestore(&dev->lock, flags);



	return PCIBIOS_SUCCESSFUL;

}



static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)

{

	struct ssb_gige *dev;

	u32 base, tmslow, tmshigh;



	dev = kzalloc(sizeof(*dev), GFP_KERNEL);

	if (!dev)

		return -ENOMEM;

	dev->dev = sdev;



	spin_lock_init(&dev->lock);

	dev->pci_controller.pci_ops = &dev->pci_ops;

	dev->pci_controller.io_resource = &dev->io_resource;

	dev->pci_controller.mem_resource = &dev->mem_resource;

	dev->pci_controller.io_map_base = 0x800;

	dev->pci_ops.read = ssb_gige_pci_read_config;

	dev->pci_ops.write = ssb_gige_pci_write_config;



	dev->io_resource.name = SSB_GIGE_IO_RES_NAME;

	dev->io_resource.start = 0x800;

	dev->io_resource.end = 0x8FF;

	dev->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;



	if (!ssb_device_is_enabled(sdev))

		ssb_device_enable(sdev, 0);



	/* Setup BAR0. This is a 64k MMIO region. */

	base = ssb_admatch_base(ssb_read32(sdev, SSB_ADMATCH1));

	gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_0, base);

	gige_pcicfg_write32(dev, PCI_BASE_ADDRESS_1, 0);



	dev->mem_resource.name = SSB_GIGE_MEM_RES_NAME;

	dev->mem_resource.start = base;

	dev->mem_resource.end = base + 0x10000 - 1;

	dev->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;



	/* Enable the memory region. */

	gige_pcicfg_write16(dev, PCI_COMMAND,

			    gige_pcicfg_read16(dev, PCI_COMMAND)

			    | PCI_COMMAND_MEMORY);



	/* Write flushing is controlled by the Flush Status Control register.

	 * We want to flush every register write with a timeout and we want

	 * to disable the IRQ mask while flushing to avoid concurrency.

	 * Note that automatic write flushing does _not_ work from

	 * an IRQ handler. The driver must flush manually by reading a register.

	 */

	gige_write32(dev, SSB_GIGE_SHIM_FLUSHSTAT, 0x00000068);



	/* Check if we have an RGMII or GMII PHY-bus.

	 * On RGMII do not bypass the DLLs */

	tmslow = ssb_read32(sdev, SSB_TMSLOW);

	tmshigh = ssb_read32(sdev, SSB_TMSHIGH);

	if (tmshigh & SSB_GIGE_TMSHIGH_RGMII) {

		tmslow &= ~SSB_GIGE_TMSLOW_TXBYPASS;

		tmslow &= ~SSB_GIGE_TMSLOW_RXBYPASS;

		dev->has_rgmii = 1;

	} else {

		tmslow |= SSB_GIGE_TMSLOW_TXBYPASS;

		tmslow |= SSB_GIGE_TMSLOW_RXBYPASS;

		dev->has_rgmii = 0;

	}

	tmslow |= SSB_GIGE_TMSLOW_DLLEN;

	ssb_write32(sdev, SSB_TMSLOW, tmslow);



	ssb_set_drvdata(sdev, dev);

	register_pci_controller(&dev->pci_controller);



	return 0;

}



bool pdev_is_ssb_gige_core(struct pci_dev *pdev)

{

	if (!pdev->resource[0].name)

		return 0;

	return (strcmp(pdev->resource[0].name, SSB_GIGE_MEM_RES_NAME) == 0);

}

EXPORT_SYMBOL(pdev_is_ssb_gige_core);



int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,

				   struct pci_dev *pdev)

{

	struct ssb_gige *dev = ssb_get_drvdata(sdev);

	struct resource *res;



	if (pdev->bus->ops != &dev->pci_ops) {

		/* The PCI device is not on this SSB GigE bridge device. */

		return -ENODEV;

	}



	/* Fixup the PCI resources. */

	res = &(pdev->resource[0]);

	res->flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;

	res->name = dev->mem_resource.name;

	res->start = dev->mem_resource.start;

	res->end = dev->mem_resource.end;



	/* Fixup interrupt lines. */

	pdev->irq = ssb_mips_irq(sdev) + 2;

	pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq);



	return 0;

}



int ssb_gige_map_irq(struct ssb_device *sdev,

		     const struct pci_dev *pdev)

{

	struct ssb_gige *dev = ssb_get_drvdata(sdev);



	if (pdev->bus->ops != &dev->pci_ops) {

		/* The PCI device is not on this SSB GigE bridge device. */

		return -ENODEV;

	}



	return ssb_mips_irq(sdev) + 2;

}



static struct ssb_driver ssb_gige_driver = {

	.name		= "BCM-GigE",

	.id_table	= ssb_gige_tbl,

	.probe		= ssb_gige_probe,

};



int ssb_gige_init(void)

{

	return ssb_driver_register(&ssb_gige_driver);

}

drivers/ssb/driver_mipscore.c

+1 −0
Original line number Diff line number Diff line
@@ -209,6 +209,7 @@ void ssb_mipscore_init(struct ssb_mipscore *mcore) 
			/* fallthrough */

		case SSB_DEV_PCI:

		case SSB_DEV_ETHERNET:

		case SSB_DEV_ETHERNET_GBIT:

		case SSB_DEV_80211:

		case SSB_DEV_USB20_HOST:

			/* These devices get their own IRQ line if available, the rest goes on IRQ0 */

drivers/ssb/driver_pcicore.c

+89 −71
Original line number Diff line number Diff line
@@ -60,77 +60,6 @@ static DEFINE_SPINLOCK(cfgspace_lock); 
/* Core to access the external PCI config space. Can only have one. */

static struct ssb_pcicore *extpci_core;



static u32 ssb_pcicore_pcibus_iobase = 0x100;

static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;



int pcibios_plat_dev_init(struct pci_dev *d)

{

	struct resource *res;

	int pos, size;

	u32 *base;



	ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",

		   pci_name(d));



	/* Fix up resource bases */

	for (pos = 0; pos < 6; pos++) {

		res = &d->resource[pos];

		if (res->flags & IORESOURCE_IO)

			base = &ssb_pcicore_pcibus_iobase;

		else

			base = &ssb_pcicore_pcibus_membase;

		res->flags |= IORESOURCE_PCI_FIXED;

		if (res->end) {

			size = res->end - res->start + 1;

			if (*base & (size - 1))

				*base = (*base + size) & ~(size - 1);

			res->start = *base;

			res->end = res->start + size - 1;

			*base += size;

			pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);

		}

		/* Fix up PCI bridge BAR0 only */

		if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)

			break;

	}

	/* Fix up interrupt lines */

	d->irq = ssb_mips_irq(extpci_core->dev) + 2;

	pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);



	return 0;

}



static void __init ssb_fixup_pcibridge(struct pci_dev *dev)

{

	u8 lat;



	if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)

		return;



	ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));



	/* Enable PCI bridge bus mastering and memory space */

	pci_set_master(dev);

	if (pcibios_enable_device(dev, ~0) < 0) {

		ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");

		return;

	}



	/* Enable PCI bridge BAR1 prefetch and burst */

	pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);



	/* Make sure our latency is high enough to handle the devices behind us */

	lat = 168;

	ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",

		   pci_name(dev), lat);

	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);

}

DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);



int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)

{

	return ssb_mips_irq(extpci_core->dev) + 2;

}



static u32 get_cfgspace_addr(struct ssb_pcicore *pc,

			     unsigned int bus, unsigned int dev,
@@ -320,6 +249,95 @@ static struct pci_controller ssb_pcicore_controller = { 
	.mem_offset	= 0x24000000,

};



static u32 ssb_pcicore_pcibus_iobase = 0x100;

static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;



/* This function is called when doing a pci_enable_device().

 * We must first check if the device is a device on the PCI-core bridge. */

int ssb_pcicore_plat_dev_init(struct pci_dev *d)

{

	struct resource *res;

	int pos, size;

	u32 *base;



	if (d->bus->ops != &ssb_pcicore_pciops) {

		/* This is not a device on the PCI-core bridge. */

		return -ENODEV;

	}



	ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",

		   pci_name(d));



	/* Fix up resource bases */

	for (pos = 0; pos < 6; pos++) {

		res = &d->resource[pos];

		if (res->flags & IORESOURCE_IO)

			base = &ssb_pcicore_pcibus_iobase;

		else

			base = &ssb_pcicore_pcibus_membase;

		res->flags |= IORESOURCE_PCI_FIXED;

		if (res->end) {

			size = res->end - res->start + 1;

			if (*base & (size - 1))

				*base = (*base + size) & ~(size - 1);

			res->start = *base;

			res->end = res->start + size - 1;

			*base += size;

			pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);

		}

		/* Fix up PCI bridge BAR0 only */

		if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)

			break;

	}

	/* Fix up interrupt lines */

	d->irq = ssb_mips_irq(extpci_core->dev) + 2;

	pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);



	return 0;

}



/* Early PCI fixup for a device on the PCI-core bridge. */

static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev)

{

	u8 lat;



	if (dev->bus->ops != &ssb_pcicore_pciops) {

		/* This is not a device on the PCI-core bridge. */

		return;

	}

	if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)

		return;



	ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));



	/* Enable PCI bridge bus mastering and memory space */

	pci_set_master(dev);

	if (pcibios_enable_device(dev, ~0) < 0) {

		ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");

		return;

	}



	/* Enable PCI bridge BAR1 prefetch and burst */

	pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);



	/* Make sure our latency is high enough to handle the devices behind us */

	lat = 168;

	ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",

		   pci_name(dev), lat);

	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);

}

DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);



/* PCI device IRQ mapping. */

int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)

{

	if (dev->bus->ops != &ssb_pcicore_pciops) {

		/* This is not a device on the PCI-core bridge. */

		return -ENODEV;

	}

	return ssb_mips_irq(extpci_core->dev) + 2;

}



static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)

{

	u32 val;