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Commit aa6865d8 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull m68k updates from Geert Uytterhoeven.

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k:
  m68k: Fix misspellings in comments.
  m68k: Use conventional function parameters for do_sigreturn
  zorro: Use kobj_to_dev()
parents 72aafdf0 efbec135
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+3 −3
Original line number Diff line number Diff line
@@ -798,7 +798,7 @@

/**********
 *
 * 0xFFFFF7xx -- Serial Periferial Interface Slave (SPIS)
 * 0xFFFFF7xx -- Serial Peripheral Interface Slave (SPIS)
 *
 **********/

@@ -824,7 +824,7 @@

/**********
 *
 * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
 * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
 *
 **********/

@@ -904,7 +904,7 @@

#define UBAUD_PRESCALER_MASK	0x003f	/* Actual divisor is 65 - PRESCALER */
#define UBAUD_PRESCALER_SHIFT	0
#define UBAUD_DIVIDE_MASK	0x0700	/* Baud Rate freq. divizor */
#define UBAUD_DIVIDE_MASK	0x0700	/* Baud Rate freq. divisor */
#define UBAUD_DIVIDE_SHIFT	8
#define UBAUD_BAUD_SRC		0x0800	/* Baud Rate Source */
#define UBAUD_GPIOSRC		0x1000	/* GPIO source */
+3 −3
Original line number Diff line number Diff line
@@ -631,7 +631,7 @@

/**********
 *
 * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
 * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
 *
 **********/

@@ -712,7 +712,7 @@

#define UBAUD_PRESCALER_MASK	0x003f	/* Actual divisor is 65 - PRESCALER */
#define UBAUD_PRESCALER_SHIFT	0
#define UBAUD_DIVIDE_MASK	0x0700	/* Baud Rate freq. divizor */
#define UBAUD_DIVIDE_MASK	0x0700	/* Baud Rate freq. divisor */
#define UBAUD_DIVIDE_SHIFT	8
#define UBAUD_BAUD_SRC		0x0800	/* Baud Rate Source */
#define UBAUD_UCLKDIR		0x2000	/* UCLK Direction */
@@ -1160,7 +1160,7 @@ typedef volatile struct {
#define DRAMMC_COL10		0x0080	/* Col address bit for MD10 PA11/PA0  */
#define DRAMMC_COL9		0x0040	/* Col address bit for MD9  PA10/PA0  */
#define DRAMMC_COL8		0x0020	/* Col address bit for MD8  PA9/PA0   */
#define DRAMMC_REF_MASK		0x001f	/* Reresh Cycle */
#define DRAMMC_REF_MASK		0x001f	/* Refresh Cycle */
#define DRAMMC_REF_SHIFT	0

/*
+3 −3
Original line number Diff line number Diff line
@@ -724,7 +724,7 @@

/**********
 *
 * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
 * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
 *
 **********/

@@ -806,7 +806,7 @@

#define UBAUD_PRESCALER_MASK	0x003f	/* Actual divisor is 65 - PRESCALER */
#define UBAUD_PRESCALER_SHIFT	0
#define UBAUD_DIVIDE_MASK	0x0700	/* Baud Rate freq. divizor */
#define UBAUD_DIVIDE_MASK	0x0700	/* Baud Rate freq. divisor */
#define UBAUD_DIVIDE_SHIFT	8
#define UBAUD_BAUD_SRC		0x0800	/* Baud Rate Source */
#define UBAUD_UCLKDIR		0x2000	/* UCLK Direction */
@@ -1256,7 +1256,7 @@ typedef struct {
#define DRAMMC_COL10		0x0080	/* Col address bit for MD10 PA11/PA0  */
#define DRAMMC_COL9		0x0040	/* Col address bit for MD9  PA10/PA0  */
#define DRAMMC_COL8		0x0020	/* Col address bit for MD8  PA9/PA0   */
#define DRAMMC_REF_MASK		0x001f	/* Reresh Cycle */
#define DRAMMC_REF_MASK		0x001f	/* Refresh Cycle */
#define DRAMMC_REF_SHIFT	0

/*
+2 −2
Original line number Diff line number Diff line
@@ -23,8 +23,8 @@
#define CACR_IEC	0x00008000	/* Enable instruction cache */
#define CACR_DNFB	0x00002000	/* Inhibited fill buffer */
#define CACR_IDPI	0x00001000	/* Disable CPUSHL */
#define CACR_IHLCK	0x00000800	/* Intruction cache half lock */
#define CACR_IDCM	0x00000400	/* Intruction cache inhibit */
#define CACR_IHLCK	0x00000800	/* Instruction cache half lock */
#define CACR_IDCM	0x00000400	/* Instruction cache inhibit */
#define CACR_ICINVA	0x00000100	/* Invalidate instr cache */
#define CACR_EUSP	0x00000020	/* Enable separate user a7 */

+1 −1
Original line number Diff line number Diff line
@@ -48,7 +48,7 @@

/* IOP message status codes */

#define IOP_MSGSTATUS_UNUSED	0	/* Unusued message structure       */
#define IOP_MSGSTATUS_UNUSED	0	/* Unused message structure        */
#define IOP_MSGSTATUS_WAITING	1	/* waiting for channel             */
#define IOP_MSGSTATUS_SENT	2	/* message sent, awaiting reply    */
#define IOP_MSGSTATUS_COMPLETE	3	/* message complete and reply rcvd */
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