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Commit aa1fbc71 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

serial: remove blackfin drivers 



The blackfin architecture is getting removed, so both the bfin_uart
and bfin_sport_uart can be removed as well.

Acked-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: default avatarAaron Wu <aaron.wu@analog.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent aa4afa2c

drivers/tty/serial/Kconfig

+0 −149
Original line number Diff line number Diff line
@@ -498,92 +498,6 @@ config SERIAL_SA1100_CONSOLE 
	  your boot loader (lilo or loadlin) about how to pass options to the

	  kernel at boot time.)



config SERIAL_BFIN

	tristate "Blackfin serial port support"

	depends on BLACKFIN

	select SERIAL_CORE

	select SERIAL_BFIN_UART0 if (BF531 || BF532 || BF533 || BF561)

	help

	  Add support for the built-in UARTs on the Blackfin.



	  To compile this driver as a module, choose M here: the

	  module is named bfin_uart.ko.



config SERIAL_BFIN_CONSOLE

	bool "Console on Blackfin serial port"

	depends on SERIAL_BFIN=y

	select SERIAL_CORE_CONSOLE



choice

	prompt "UART Mode"

	depends on SERIAL_BFIN

	default SERIAL_BFIN_DMA

	help

	  This driver supports the built-in serial ports of the Blackfin family

	  of CPUs



config SERIAL_BFIN_DMA

	bool "DMA mode"

	depends on !DMA_UNCACHED_NONE && KGDB_SERIAL_CONSOLE=n

	help

	  This driver works under DMA mode. If this option is selected, the

	  blackfin simple dma driver is also enabled.



config SERIAL_BFIN_PIO

	bool "PIO mode"

	help

	  This driver works under PIO mode.



endchoice



config SERIAL_BFIN_UART0

	bool "Enable UART0"

	depends on SERIAL_BFIN

	help

	  Enable UART0



config BFIN_UART0_CTSRTS

	bool "Enable UART0 hardware flow control"

	depends on SERIAL_BFIN_UART0

	help

	  Enable hardware flow control in the driver.



config SERIAL_BFIN_UART1

	bool "Enable UART1"

	depends on SERIAL_BFIN && (!BF531 && !BF532 && !BF533 && !BF561)

	help

	  Enable UART1



config BFIN_UART1_CTSRTS

	bool "Enable UART1 hardware flow control"

	depends on SERIAL_BFIN_UART1

	help

	  Enable hardware flow control in the driver.



config SERIAL_BFIN_UART2

	bool "Enable UART2"

	depends on SERIAL_BFIN && (BF54x || BF538 || BF539)

	help

	  Enable UART2



config BFIN_UART2_CTSRTS

	bool "Enable UART2 hardware flow control"

	depends on SERIAL_BFIN_UART2

	help

	  Enable hardware flow control in the driver.



config SERIAL_BFIN_UART3

	bool "Enable UART3"

	depends on SERIAL_BFIN && (BF54x)

	help

	  Enable UART3



config BFIN_UART3_CTSRTS

	bool "Enable UART3 hardware flow control"

	depends on SERIAL_BFIN_UART3

	help

	  Enable hardware flow control in the driver.



config SERIAL_IMX

	tristate "IMX serial port support"

	depends on HAS_DMA
@@ -1231,69 +1145,6 @@ config SERIAL_SC16IS7XX_SPI 
          This is additional support to exsisting driver.

          You must select at least one bus for the driver to be built.



config SERIAL_BFIN_SPORT

	tristate "Blackfin SPORT emulate UART"

	depends on BLACKFIN

	select SERIAL_CORE

	help

	  Enable SPORT emulate UART on Blackfin series.



	  To compile this driver as a module, choose M here: the

	  module will be called bfin_sport_uart.



config SERIAL_BFIN_SPORT_CONSOLE

	bool "Console on Blackfin sport emulated uart"

	depends on SERIAL_BFIN_SPORT=y

	select SERIAL_CORE_CONSOLE



config SERIAL_BFIN_SPORT0_UART

	bool "Enable UART over SPORT0"

	depends on SERIAL_BFIN_SPORT && !(BF542 || BF544)

	help

	  Enable UART over SPORT0



config SERIAL_BFIN_SPORT0_UART_CTSRTS

	bool "Enable UART over SPORT0 hardware flow control"

	depends on SERIAL_BFIN_SPORT0_UART

	help

	  Enable hardware flow control in the driver.



config SERIAL_BFIN_SPORT1_UART

	bool "Enable UART over SPORT1"

	depends on SERIAL_BFIN_SPORT

	help

	  Enable UART over SPORT1



config SERIAL_BFIN_SPORT1_UART_CTSRTS

	bool "Enable UART over SPORT1 hardware flow control"

	depends on SERIAL_BFIN_SPORT1_UART

	help

	  Enable hardware flow control in the driver.



config SERIAL_BFIN_SPORT2_UART

	bool "Enable UART over SPORT2"

	depends on SERIAL_BFIN_SPORT && (BF54x || BF538 || BF539)

	help

	  Enable UART over SPORT2



config SERIAL_BFIN_SPORT2_UART_CTSRTS

	bool "Enable UART over SPORT2 hardware flow control"

	depends on SERIAL_BFIN_SPORT2_UART

	help

	  Enable hardware flow control in the driver.



config SERIAL_BFIN_SPORT3_UART

	bool "Enable UART over SPORT3"

	depends on SERIAL_BFIN_SPORT && (BF54x || BF538 || BF539)

	help

	  Enable UART over SPORT3



config SERIAL_BFIN_SPORT3_UART_CTSRTS

	bool "Enable UART over SPORT3 hardware flow control"

	depends on SERIAL_BFIN_SPORT3_UART

	help

	  Enable hardware flow control in the driver.



config SERIAL_TIMBERDALE

	tristate "Support for timberdale UART"

	select SERIAL_CORE

drivers/tty/serial/Makefile

+0 −2
Original line number Diff line number Diff line
@@ -29,8 +29,6 @@ obj-$(CONFIG_SERIAL_PXA_NON8250) += pxa.o 
obj-$(CONFIG_SERIAL_PNX8XXX) += pnx8xxx_uart.o

obj-$(CONFIG_SERIAL_SA1100) += sa1100.o

obj-$(CONFIG_SERIAL_BCM63XX) += bcm63xx_uart.o

obj-$(CONFIG_SERIAL_BFIN) += bfin_uart.o

obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o

obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o

obj-$(CONFIG_SERIAL_MAX3100) += max3100.o

obj-$(CONFIG_SERIAL_MAX310X) += max310x.o

drivers/tty/serial/bfin_sport_uart.c

deleted100644 → 0
+0 −937

File deleted.

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drivers/tty/serial/bfin_sport_uart.h

deleted100644 → 0
+0 −86
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0+

/*

 * Blackfin On-Chip Sport Emulated UART Driver

 *

 * Copyright 2006-2008 Analog Devices Inc.

 *

 * Enter bugs at http://blackfin.uclinux.org/

 */



/*

 * This driver and the hardware supported are in term of EE-191 of ADI.

 * http://www.analog.com/static/imported-files/application_notes/EE191.pdf 

 * This application note describe how to implement a UART on a Sharc DSP,

 * but this driver is implemented on Blackfin Processor.

 * Transmit Frame Sync is not used by this driver to transfer data out.

 */



#ifndef _BFIN_SPORT_UART_H

#define _BFIN_SPORT_UART_H



#define OFFSET_TCR1		0x00	/* Transmit Configuration 1 Register */

#define OFFSET_TCR2		0x04	/* Transmit Configuration 2 Register */

#define OFFSET_TCLKDIV		0x08	/* Transmit Serial Clock Divider Register */

#define OFFSET_TFSDIV		0x0C	/* Transmit Frame Sync Divider Register */

#define OFFSET_TX		0x10	/* Transmit Data Register		*/

#define OFFSET_RX		0x18	/* Receive Data Register		*/

#define OFFSET_RCR1		0x20	/* Receive Configuration 1 Register	*/

#define OFFSET_RCR2		0x24	/* Receive Configuration 2 Register	*/

#define OFFSET_RCLKDIV		0x28	/* Receive Serial Clock Divider Register */

#define OFFSET_RFSDIV		0x2c	/* Receive Frame Sync Divider Register */

#define OFFSET_STAT		0x30	/* Status Register			*/



#define SPORT_GET_TCR1(sport)		bfin_read16(((sport)->port.membase + OFFSET_TCR1))

#define SPORT_GET_TCR2(sport)		bfin_read16(((sport)->port.membase + OFFSET_TCR2))

#define SPORT_GET_TCLKDIV(sport)	bfin_read16(((sport)->port.membase + OFFSET_TCLKDIV))

#define SPORT_GET_TFSDIV(sport)		bfin_read16(((sport)->port.membase + OFFSET_TFSDIV))

#define SPORT_GET_TX(sport)		bfin_read16(((sport)->port.membase + OFFSET_TX))

#define SPORT_GET_RX(sport)		bfin_read16(((sport)->port.membase + OFFSET_RX))

/*

 * If another interrupt fires while doing a 32-bit read from RX FIFO,

 * a fake RX underflow error will be generated.  So disable interrupts

 * to prevent interruption while reading the FIFO.

 */

#define SPORT_GET_RX32(sport) \

({ \

	unsigned int __ret; \

	unsigned long flags; \

	if (ANOMALY_05000473) \

		local_irq_save(flags); \

	__ret = bfin_read32((sport)->port.membase + OFFSET_RX); \

	if (ANOMALY_05000473) \

		local_irq_restore(flags); \

	__ret; \

})

#define SPORT_GET_RCR1(sport)		bfin_read16(((sport)->port.membase + OFFSET_RCR1))

#define SPORT_GET_RCR2(sport)		bfin_read16(((sport)->port.membase + OFFSET_RCR2))

#define SPORT_GET_RCLKDIV(sport)	bfin_read16(((sport)->port.membase + OFFSET_RCLKDIV))

#define SPORT_GET_RFSDIV(sport)		bfin_read16(((sport)->port.membase + OFFSET_RFSDIV))

#define SPORT_GET_STAT(sport)		bfin_read16(((sport)->port.membase + OFFSET_STAT))



#define SPORT_PUT_TCR1(sport, v)	bfin_write16(((sport)->port.membase + OFFSET_TCR1), v)

#define SPORT_PUT_TCR2(sport, v)	bfin_write16(((sport)->port.membase + OFFSET_TCR2), v)

#define SPORT_PUT_TCLKDIV(sport, v)	bfin_write16(((sport)->port.membase + OFFSET_TCLKDIV), v)

#define SPORT_PUT_TFSDIV(sport, v)	bfin_write16(((sport)->port.membase + OFFSET_TFSDIV), v)

#define SPORT_PUT_TX(sport, v)		bfin_write16(((sport)->port.membase + OFFSET_TX), v)

#define SPORT_PUT_RX(sport, v)		bfin_write16(((sport)->port.membase + OFFSET_RX), v)

#define SPORT_PUT_RCR1(sport, v)	bfin_write16(((sport)->port.membase + OFFSET_RCR1), v)

#define SPORT_PUT_RCR2(sport, v)	bfin_write16(((sport)->port.membase + OFFSET_RCR2), v)

#define SPORT_PUT_RCLKDIV(sport, v)	bfin_write16(((sport)->port.membase + OFFSET_RCLKDIV), v)

#define SPORT_PUT_RFSDIV(sport, v)	bfin_write16(((sport)->port.membase + OFFSET_RFSDIV), v)

#define SPORT_PUT_STAT(sport, v)	bfin_write16(((sport)->port.membase + OFFSET_STAT), v)



#define SPORT_TX_FIFO_SIZE	8



#define SPORT_UART_GET_CTS(x)		gpio_get_value(x->cts_pin)

#define SPORT_UART_DISABLE_RTS(x)	gpio_set_value(x->rts_pin, 1)

#define SPORT_UART_ENABLE_RTS(x)	gpio_set_value(x->rts_pin, 0)



#if defined(CONFIG_SERIAL_BFIN_SPORT0_UART_CTSRTS) \

	|| defined(CONFIG_SERIAL_BFIN_SPORT1_UART_CTSRTS) \

	|| defined(CONFIG_SERIAL_BFIN_SPORT2_UART_CTSRTS) \

	|| defined(CONFIG_SERIAL_BFIN_SPORT3_UART_CTSRTS)

# define CONFIG_SERIAL_BFIN_SPORT_CTSRTS

#endif



#endif /* _BFIN_SPORT_UART_H */

drivers/tty/serial/bfin_uart.c

deleted100644 → 0
+0 −1551

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