Merge branch 'sh/urgent' into sh-fixes-for-linus (a9fc7492) · Commits · e / devices / android_kernel_oneplus_sm7250

arch/sh/boards/mach-se/7724/setup.c

+5 −38

Original line number	Diff line number	Diff line
		@@ -283,31 +283,6 @@ static struct platform_device ceu1_device = {
		};

		/* FSI */
		/*
		* FSI-A use external clock which came from ak464x.
		* So, we should change parent of fsi
		*/
		#define FCLKACR 0xa4150008
		static void fsimck_init(struct clk *clk)
		{
		u32 status = __raw_readl(clk->enable_reg);

		/* use external clock */
		status &= ~0x000000ff;
		status \|= 0x00000080;
		__raw_writel(status, clk->enable_reg);
		}

		static struct clk_ops fsimck_clk_ops = {
		.init = fsimck_init,
		};

		static struct clk fsimcka_clk = {
		.ops = &fsimck_clk_ops,
		.enable_reg = (void __iomem *)FCLKACR,
		.rate = 0, /* unknown */
		};

		/* change J20, J21, J22 pin to 1-2 connection to use slave mode */
		static struct sh_fsi_platform_info fsi_info = {
		.porta_flags = SH_FSI_BRS_INV \|
		@@ -852,22 +827,14 @@ static int __init devices_setup(void)
		gpio_request(GPIO_FN_KEYOUT0, NULL);

		/* enable FSI */
		gpio_request(GPIO_FN_FSIMCKB, NULL);
		gpio_request(GPIO_FN_FSIMCKA, NULL);
		gpio_request(GPIO_FN_FSIIASD, NULL);
		gpio_request(GPIO_FN_FSIOASD, NULL);
		gpio_request(GPIO_FN_FSIIABCK, NULL);
		gpio_request(GPIO_FN_FSIIALRCK, NULL);
		gpio_request(GPIO_FN_FSIOABCK, NULL);
		gpio_request(GPIO_FN_FSIOALRCK, NULL);
		gpio_request(GPIO_FN_CLKAUDIOAO, NULL);
		gpio_request(GPIO_FN_FSIIBSD, NULL);
		gpio_request(GPIO_FN_FSIOBSD, NULL);
		gpio_request(GPIO_FN_FSIIBBCK, NULL);
		gpio_request(GPIO_FN_FSIIBLRCK, NULL);
		gpio_request(GPIO_FN_FSIOBBCK, NULL);
		gpio_request(GPIO_FN_FSIOBLRCK, NULL);
		gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
		gpio_request(GPIO_FN_FSIIASD, NULL);

		/* set SPU2 clock to 83.4 MHz */
		clk = clk_get(NULL, "spu_clk");
		@@ -879,10 +846,10 @@ static int __init devices_setup(void)
		/* change parent of FSI A */
		clk = clk_get(NULL, "fsia_clk");
		if (!IS_ERR(clk)) {
		clk_register(&fsimcka_clk);
		clk_set_parent(clk, &fsimcka_clk);
		clk_set_rate(clk, 11000);
		clk_set_rate(&fsimcka_clk, 11000);
		/* 48kHz dummy clock was used to make sure 1/1 divide */
		clk_set_rate(&sh7724_fsimcka_clk, 48000);
		clk_set_parent(clk, &sh7724_fsimcka_clk);
		clk_set_rate(clk, 48000);
		clk_put(clk);
		}