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Commit a9f3cf01 authored by Udipto Goswami's avatar Udipto Goswami
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ARM: dts: msm: Add AHB2PHY Clock for Khaje

Add AHB2PHY clock for Khaje since required for
HS & SS PHY. Without the clock we might run into
unclocked access issues in APSS suspend.

Change-Id: I581be5ce1ebcdaa105d0d4a0f4e1f1729c31c46b
parent f0f0d894
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+7 −4
Original line number Diff line number Diff line
@@ -138,8 +138,9 @@
		vdda33-supply = <&L15A>;
		qcom,vdd-voltage-level = <0 880000 880000>;

		clocks = <&rpmcc CXO_SMD_OTG_CLK>;
		clock-names =  "ref_clk_src";
		clocks = <&rpmcc CXO_SMD_OTG_CLK>,
			<&gcc GCC_AHB2PHY_USB_CLK>;
		clock-names =  "ref_clk_src", "cfg_ahb_clk";

		resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
		reset-names = "phy_reset";
@@ -163,10 +164,12 @@
			 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
			 <&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
			 <&rpmcc CXO_SMD_OTG_CLK>,
			 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
			 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
			 <&gcc GCC_AHB2PHY_USB_CLK>;

		clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
				"pipe_clk_ext_src", "ref_clk_src",
				"com_aux_clk";
				"com_aux_clk","cfg_ahb_clk";

		resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
			 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;