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Commit a97703c5 authored by Gabriel Fernandez's avatar Gabriel Fernandez Committed by Michael Turquette
Browse files

clk: stm32mp1: add Post-dividers for PLL 



Each PLL has 3 outputs with post-dividers.

pll1_p is dedicated for Cortex-A7
pll1_q is not connected
pll1_r is not connected

pll2_p is dedicated for AXI
pll2_q is dedicated for GPU
pll2_r is dedicated for DDR

pll3_p is dedicated for mcu
pll3_q is for Peripheral Kernel Clock
pll3_r is for Peripheral Kernel Clock

pll4_p is for Peripheral Kernel Clock
pll4_q is for Peripheral Kernel Clock
pll4_r is for Peripheral Kernel Clock

Signed-off-by: default avatarGabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
parent c6cf4d32

drivers/clk/clk-stm32mp1.c

+221 −0
Original line number Diff line number Diff line
@@ -166,6 +166,23 @@ struct stm32_gate_cfg { 
	const struct clk_ops	*ops;

};



struct stm32_div_cfg {

	struct div_cfg		*div;

	const struct clk_ops	*ops;

};



struct stm32_mux_cfg {

	struct mux_cfg		*mux;

	const struct clk_ops	*ops;

};



/* STM32 Composite clock */

struct stm32_composite_cfg {

	const struct stm32_gate_cfg	*gate;

	const struct stm32_div_cfg	*div;

	const struct stm32_mux_cfg	*mux;

};



static struct clk_hw *

_clk_hw_register_gate(struct device *dev,

		      struct clk_hw_onecell_data *clk_data,
@@ -259,6 +276,51 @@ const struct clk_ops mp1_gate_clk_ops = { 
	.is_enabled	= clk_gate_is_enabled,

};



static struct clk_hw *_get_stm32_mux(void __iomem *base,

				     const struct stm32_mux_cfg *cfg,

				     spinlock_t *lock)

{

	struct clk_mux *mux;

	struct clk_hw *mux_hw;



	mux = kzalloc(sizeof(*mux), GFP_KERNEL);

	if (!mux)

		return ERR_PTR(-ENOMEM);



	mux->reg = cfg->mux->reg_off + base;

	mux->shift = cfg->mux->shift;

	mux->mask = (1 << cfg->mux->width) - 1;

	mux->flags = cfg->mux->mux_flags;

	mux->table = cfg->mux->table;



	mux->lock = lock;



	mux_hw = &mux->hw;



	return mux_hw;

}



static struct clk_hw *_get_stm32_div(void __iomem *base,

				     const struct stm32_div_cfg *cfg,

				     spinlock_t *lock)

{

	struct clk_divider *div;



	div = kzalloc(sizeof(*div), GFP_KERNEL);



	if (!div)

		return ERR_PTR(-ENOMEM);



	div->reg = cfg->div->reg_off + base;

	div->shift = cfg->div->shift;

	div->width = cfg->div->width;

	div->flags = cfg->div->div_flags;

	div->table = cfg->div->table;

	div->lock = lock;



	return &div->hw;

}



static struct clk_hw *

_get_stm32_gate(void __iomem *base,

		const struct stm32_gate_cfg *cfg, spinlock_t *lock)
@@ -322,6 +384,61 @@ clk_stm32_register_gate_ops(struct device *dev, 
	return hw;

}



static struct clk_hw *

clk_stm32_register_composite(struct device *dev,

			     const char *name, const char * const *parent_names,

			     int num_parents, void __iomem *base,

			     const struct stm32_composite_cfg *cfg,

			     unsigned long flags, spinlock_t *lock)

{

	const struct clk_ops *mux_ops, *div_ops, *gate_ops;

	struct clk_hw *mux_hw, *div_hw, *gate_hw;



	mux_hw = NULL;

	div_hw = NULL;

	gate_hw = NULL;

	mux_ops = NULL;

	div_ops = NULL;

	gate_ops = NULL;



	if (cfg->mux) {

		mux_hw = _get_stm32_mux(base, cfg->mux, lock);



		if (!IS_ERR(mux_hw)) {

			mux_ops = &clk_mux_ops;



			if (cfg->mux->ops)

				mux_ops = cfg->mux->ops;

		}

	}



	if (cfg->div) {

		div_hw = _get_stm32_div(base, cfg->div, lock);



		if (!IS_ERR(div_hw)) {

			div_ops = &clk_divider_ops;



			if (cfg->div->ops)

				div_ops = cfg->div->ops;

		}

	}



	if (cfg->gate) {

		gate_hw = _get_stm32_gate(base, cfg->gate, lock);



		if (!IS_ERR(gate_hw)) {

			gate_ops = &clk_gate_ops;



			if (cfg->gate->ops)

				gate_ops = cfg->gate->ops;

		}

	}



	return clk_hw_register_composite(dev, name, parent_names, num_parents,

				       mux_hw, mux_ops, div_hw, div_ops,

				       gate_hw, gate_ops, flags);

}



/* STM32 PLL */



struct stm32_pll_obj {
@@ -527,6 +644,17 @@ _clk_stm32_register_gate(struct device *dev, 
				    lock);

}



static struct clk_hw *

_clk_stm32_register_composite(struct device *dev,

			      struct clk_hw_onecell_data *clk_data,

			      void __iomem *base, spinlock_t *lock,

			      const struct clock_config *cfg)

{

	return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names,

					    cfg->num_parents, base, cfg->cfg,

					    cfg->flags, lock);

}



#define GATE(_id, _name, _parent, _flags, _offset, _bit_idx, _gate_flags)\

{\

	.id		= _id,\
@@ -624,6 +752,10 @@ _clk_stm32_register_gate(struct device *dev, 
		.ops		= _ops,\

	})



#define _GATE(_gate_offset, _gate_bit_idx, _gate_flags)\

	_STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\

		    NULL)\



#define _GATE_MP1(_gate_offset, _gate_bit_idx, _gate_flags)\

	_STM32_GATE(_gate_offset, _gate_bit_idx, _gate_flags,\

		    &mp1_gate_clk_ops)\
@@ -632,6 +764,44 @@ _clk_stm32_register_gate(struct device *dev, 
	STM32_GATE(_id, _name, _parent, _flags,\

		   _GATE_MP1(_offset, _bit_idx, _gate_flags))



#define _STM32_DIV(_div_offset, _div_shift, _div_width,\

		   _div_flags, _div_table, _ops)\

	.div = &(struct stm32_div_cfg) {\

		&(struct div_cfg) {\

			.reg_off	= _div_offset,\

			.shift		= _div_shift,\

			.width		= _div_width,\

			.div_flags	= _div_flags,\

			.table		= _div_table,\

		},\

		.ops		= _ops,\

	}



#define _DIV(_div_offset, _div_shift, _div_width, _div_flags, _div_table)\

	_STM32_DIV(_div_offset, _div_shift, _div_width,\

		   _div_flags, _div_table, NULL)\



#define PARENT(_parent) ((const char *[]) { _parent})



#define _NO_MUX .mux = NULL

#define _NO_DIV .div = NULL

#define _NO_GATE .gate = NULL



#define COMPOSITE(_id, _name, _parents, _flags, _gate, _mux, _div)\

{\

	.id		= _id,\

	.name		= _name,\

	.parent_names	= _parents,\

	.num_parents	= ARRAY_SIZE(_parents),\

	.flags		= _flags,\

	.cfg		= &(struct stm32_composite_cfg) {\

		_gate,\

		_mux,\

		_div,\

	},\

	.func		= _clk_stm32_register_composite,\

}



static const struct clock_config stm32mp1_clock_cfg[] = {

	/* Oscillator divider */

	DIV(NO_ID, "clk-hsi-div", "clk-hsi", 0, RCC_HSICFGR, 0, 2,
@@ -661,6 +831,57 @@ static const struct clock_config stm32mp1_clock_cfg[] = { 
	PLL(PLL2, "pll2", "ref1", CLK_IGNORE_UNUSED, RCC_PLL2CR),

	PLL(PLL3, "pll3", "ref3", CLK_IGNORE_UNUSED, RCC_PLL3CR),

	PLL(PLL4, "pll4", "ref4", CLK_IGNORE_UNUSED, RCC_PLL4CR),



	/* ODF */

	COMPOSITE(PLL1_P, "pll1_p", PARENT("pll1"), 0,

		  _GATE(RCC_PLL1CR, 4, 0),

		  _NO_MUX,

		  _DIV(RCC_PLL1CFGR2, 0, 7, 0, NULL)),



	COMPOSITE(PLL2_P, "pll2_p", PARENT("pll2"), 0,

		  _GATE(RCC_PLL2CR, 4, 0),

		  _NO_MUX,

		  _DIV(RCC_PLL2CFGR2, 0, 7, 0, NULL)),



	COMPOSITE(PLL2_Q, "pll2_q", PARENT("pll2"), 0,

		  _GATE(RCC_PLL2CR, 5, 0),

		  _NO_MUX,

		  _DIV(RCC_PLL2CFGR2, 8, 7, 0, NULL)),



	COMPOSITE(PLL2_R, "pll2_r", PARENT("pll2"), CLK_IS_CRITICAL,

		  _GATE(RCC_PLL2CR, 6, 0),

		  _NO_MUX,

		  _DIV(RCC_PLL2CFGR2, 16, 7, 0, NULL)),



	COMPOSITE(PLL3_P, "pll3_p", PARENT("pll3"), 0,

		  _GATE(RCC_PLL3CR, 4, 0),

		  _NO_MUX,

		  _DIV(RCC_PLL3CFGR2, 0, 7, 0, NULL)),



	COMPOSITE(PLL3_Q, "pll3_q", PARENT("pll3"), 0,

		  _GATE(RCC_PLL3CR, 5, 0),

		  _NO_MUX,

		  _DIV(RCC_PLL3CFGR2, 8, 7, 0, NULL)),



	COMPOSITE(PLL3_R, "pll3_r", PARENT("pll3"), 0,

		  _GATE(RCC_PLL3CR, 6, 0),

		  _NO_MUX,

		  _DIV(RCC_PLL3CFGR2, 16, 7, 0, NULL)),



	COMPOSITE(PLL4_P, "pll4_p", PARENT("pll4"), 0,

		  _GATE(RCC_PLL4CR, 4, 0),

		  _NO_MUX,

		  _DIV(RCC_PLL4CFGR2, 0, 7, 0, NULL)),



	COMPOSITE(PLL4_Q, "pll4_q", PARENT("pll4"), 0,

		  _GATE(RCC_PLL4CR, 5, 0),

		  _NO_MUX,

		  _DIV(RCC_PLL4CFGR2, 8, 7, 0, NULL)),



	COMPOSITE(PLL4_R, "pll4_r", PARENT("pll4"), 0,

		  _GATE(RCC_PLL4CR, 6, 0),

		  _NO_MUX,

		  _DIV(RCC_PLL4CFGR2, 16, 7, 0, NULL)),

};



struct stm32_clock_match_data {