Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a929b325 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-armada-fixes' of git://git.armlinux.org.uk/~rmk/linux-arm into drm-fixes 



Two armada fixes.

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180713075427.GA16160@rmk-PC.armlinux.org.uk
parents 99018753 92298c1c

drivers/gpu/drm/armada/armada_crtc.c

+10 −2
Original line number Diff line number Diff line
@@ -519,8 +519,9 @@ static irqreturn_t armada_drm_irq(int irq, void *arg) 
	u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);



	/*

	 * This is rediculous - rather than writing bits to clear, we

	 * have to set the actual status register value.  This is racy.

	 * Reading the ISR appears to clear bits provided CLEAN_SPU_IRQ_ISR

	 * is set.  Writing has some other effect to acknowledge the IRQ -

	 * without this, we only get a single IRQ.

	 */

	writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
@@ -1116,16 +1117,22 @@ armada_drm_crtc_set_property(struct drm_crtc *crtc, 
static int armada_drm_crtc_enable_vblank(struct drm_crtc *crtc)

{

	struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);

	unsigned long flags;



	spin_lock_irqsave(&dcrtc->irq_lock, flags);

	armada_drm_crtc_enable_irq(dcrtc, VSYNC_IRQ_ENA);

	spin_unlock_irqrestore(&dcrtc->irq_lock, flags);

	return 0;

}



static void armada_drm_crtc_disable_vblank(struct drm_crtc *crtc)

{

	struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);

	unsigned long flags;



	spin_lock_irqsave(&dcrtc->irq_lock, flags);

	armada_drm_crtc_disable_irq(dcrtc, VSYNC_IRQ_ENA);

	spin_unlock_irqrestore(&dcrtc->irq_lock, flags);

}



static const struct drm_crtc_funcs armada_crtc_funcs = {
@@ -1415,6 +1422,7 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev, 
		       CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);

	writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);

	writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);

	readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);

	writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);



	ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",

drivers/gpu/drm/armada/armada_hw.h

+1 −0
Original line number Diff line number Diff line
@@ -160,6 +160,7 @@ enum { 
	CFG_ALPHAM_GRA		= 0x1 << 16,

	CFG_ALPHAM_CFG		= 0x2 << 16,

	CFG_ALPHA_MASK		= 0xff << 8,

#define CFG_ALPHA(x)		((x) << 8)

	CFG_PIXCMD_MASK		= 0xff,

};

drivers/gpu/drm/armada/armada_overlay.c

+22 −8
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ struct armada_ovl_plane_properties { 
	uint16_t contrast;

	uint16_t saturation;

	uint32_t colorkey_mode;

	uint32_t colorkey_enable;

};



struct armada_ovl_plane {
@@ -54,11 +55,13 @@ armada_ovl_update_attr(struct armada_ovl_plane_properties *prop, 
	writel_relaxed(0x00002000, dcrtc->base + LCD_SPU_CBSH_HUE);



	spin_lock_irq(&dcrtc->irq_lock);

	armada_updatel(prop->colorkey_mode | CFG_ALPHAM_GRA,

	armada_updatel(prop->colorkey_mode,

		       CFG_CKMODE_MASK | CFG_ALPHAM_MASK | CFG_ALPHA_MASK,

		       dcrtc->base + LCD_SPU_DMA_CTRL1);



	armada_updatel(ADV_GRACOLORKEY, 0, dcrtc->base + LCD_SPU_ADV_REG);

	if (dcrtc->variant->has_spu_adv_reg)

		armada_updatel(prop->colorkey_enable,

			       ADV_GRACOLORKEY | ADV_VIDCOLORKEY,

			       dcrtc->base + LCD_SPU_ADV_REG);

	spin_unlock_irq(&dcrtc->irq_lock);

}
@@ -321,8 +324,17 @@ static int armada_ovl_plane_set_property(struct drm_plane *plane, 
		dplane->prop.colorkey_vb |= K2B(val);

		update_attr = true;

	} else if (property == priv->colorkey_mode_prop) {

		dplane->prop.colorkey_mode &= ~CFG_CKMODE_MASK;

		dplane->prop.colorkey_mode |= CFG_CKMODE(val);

		if (val == CKMODE_DISABLE) {

			dplane->prop.colorkey_mode =

				CFG_CKMODE(CKMODE_DISABLE) |

				CFG_ALPHAM_CFG | CFG_ALPHA(255);

			dplane->prop.colorkey_enable = 0;

		} else {

			dplane->prop.colorkey_mode =

				CFG_CKMODE(val) |

				CFG_ALPHAM_GRA | CFG_ALPHA(0);

			dplane->prop.colorkey_enable = ADV_GRACOLORKEY;

		}

		update_attr = true;

	} else if (property == priv->brightness_prop) {

		dplane->prop.brightness = val - 256;
@@ -453,7 +465,9 @@ int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs) 
	dplane->prop.colorkey_yr = 0xfefefe00;

	dplane->prop.colorkey_ug = 0x01010100;

	dplane->prop.colorkey_vb = 0x01010100;

	dplane->prop.colorkey_mode = CFG_CKMODE(CKMODE_RGB);

	dplane->prop.colorkey_mode = CFG_CKMODE(CKMODE_RGB) |

				     CFG_ALPHAM_GRA | CFG_ALPHA(0);

	dplane->prop.colorkey_enable = ADV_GRACOLORKEY;

	dplane->prop.brightness = 0;

	dplane->prop.contrast = 0x4000;

	dplane->prop.saturation = 0x4000;