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Commit a9261487 authored by Stefan Wahren's avatar Stefan Wahren Committed by Michael Turquette
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Revert "clk: mxs: Fix invalid 32-bit access to frac registers" 



Revert commit 039e5970 (clk: mxs: Fix invalid 32-bit access to frac
registers), because it leads to a faulty spi communication on mx28evk.

Signed-off-by: default avatarStefan Wahren <stefan.wahren@i2se.com>
Reported-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
Tested-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
parent a513b72c

drivers/clk/mxs/clk-imx23.c

+3 −8
Original line number Diff line number Diff line
@@ -46,13 +46,11 @@ static void __iomem *digctrl; 
#define BP_CLKSEQ_BYPASS_SAIF	0

#define BP_CLKSEQ_BYPASS_SSP	5

#define BP_SAIF_DIV_FRAC_EN	16



#define FRAC_IO	3

#define BP_FRAC_IOFRAC		24



static void __init clk_misc_init(void)

{

	u32 val;

	u8 frac;



	/* Gate off cpu clock in WFI for power saving */

	writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
@@ -74,12 +72,9 @@ static void __init clk_misc_init(void) 
	/*

	 * 480 MHz seems too high to be ssp clock source directly,

	 * so set frac to get a 288 MHz ref_io.

	 * According to reference manual we must access frac bytewise.

	 */

	frac = readb_relaxed(FRAC + FRAC_IO);

	frac &= ~0x3f;

	frac |= 30;

	writeb_relaxed(frac, FRAC + FRAC_IO);

	writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR);

	writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET);

}



static const char *sel_pll[]  __initconst = { "pll", "ref_xtal", };

drivers/clk/mxs/clk-imx28.c

+6 −13
Original line number Diff line number Diff line
@@ -53,9 +53,8 @@ static void __iomem *clkctrl; 
#define BP_ENET_SLEEP		31

#define BP_CLKSEQ_BYPASS_SAIF0	0

#define BP_CLKSEQ_BYPASS_SSP0	3



#define FRAC0_IO1	2

#define FRAC0_IO0	3

#define BP_FRAC0_IO1FRAC	16

#define BP_FRAC0_IO0FRAC	24



static void __iomem *digctrl;

#define DIGCTRL digctrl
@@ -86,7 +85,6 @@ int mxs_saif_clkmux_select(unsigned int clkmux) 
static void __init clk_misc_init(void)

{

	u32 val;

	u8 frac;



	/* Gate off cpu clock in WFI for power saving */

	writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
@@ -120,16 +118,11 @@ static void __init clk_misc_init(void) 
	/*

	 * 480 MHz seems too high to be ssp clock source directly,

	 * so set frac0 to get a 288 MHz ref_io0 and ref_io1.

	 * According to reference manual we must access frac0 bytewise.

	 */

	frac = readb_relaxed(FRAC0 + FRAC0_IO0);

	frac &= ~0x3f;

	frac |= 30;

	writeb_relaxed(frac, FRAC0 + FRAC0_IO0);

	frac = readb_relaxed(FRAC0 + FRAC0_IO1);

	frac &= ~0x3f;

	frac |= 30;

	writeb_relaxed(frac, FRAC0 + FRAC0_IO1);

	val = readl_relaxed(FRAC0);

	val &= ~((0x3f << BP_FRAC0_IO0FRAC) | (0x3f << BP_FRAC0_IO1FRAC));

	val |= (30 << BP_FRAC0_IO0FRAC) | (30 << BP_FRAC0_IO1FRAC);

	writel_relaxed(val, FRAC0);

}



static const char *sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };

drivers/clk/mxs/clk-ref.c

+9 −10
Original line number Diff line number Diff line
@@ -16,8 +16,6 @@ 
#include <linux/slab.h>

#include "clk.h"



#define BF_CLKGATE	BIT(7)



/**

 * struct clk_ref - mxs reference clock

 * @hw: clk_hw for the reference clock
@@ -41,7 +39,7 @@ static int clk_ref_enable(struct clk_hw *hw) 
{

	struct clk_ref *ref = to_clk_ref(hw);



	writeb_relaxed(BF_CLKGATE, ref->reg + ref->idx + CLR);

	writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + CLR);



	return 0;

}
@@ -50,7 +48,7 @@ static void clk_ref_disable(struct clk_hw *hw) 
{

	struct clk_ref *ref = to_clk_ref(hw);



	writeb_relaxed(BF_CLKGATE, ref->reg + ref->idx + SET);

	writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + SET);

}



static unsigned long clk_ref_recalc_rate(struct clk_hw *hw,
@@ -58,7 +56,7 @@ static unsigned long clk_ref_recalc_rate(struct clk_hw *hw, 
{

	struct clk_ref *ref = to_clk_ref(hw);

	u64 tmp = parent_rate;

	u8 frac = readb_relaxed(ref->reg + ref->idx) & 0x3f;

	u8 frac = (readl_relaxed(ref->reg) >> (ref->idx * 8)) & 0x3f;



	tmp *= 18;

	do_div(tmp, frac);
@@ -95,7 +93,8 @@ static int clk_ref_set_rate(struct clk_hw *hw, unsigned long rate, 
	struct clk_ref *ref = to_clk_ref(hw);

	unsigned long flags;

	u64 tmp = parent_rate;

	u8 frac, val;

	u32 val;

	u8 frac, shift = ref->idx * 8;



	tmp = tmp * 18 + rate / 2;

	do_div(tmp, rate);
@@ -108,10 +107,10 @@ static int clk_ref_set_rate(struct clk_hw *hw, unsigned long rate, 


	spin_lock_irqsave(&mxs_lock, flags);



	val = readb_relaxed(ref->reg + ref->idx);

	val &= ~0x3f;

	val |= frac;

	writeb_relaxed(val, ref->reg + ref->idx);

	val = readl_relaxed(ref->reg);

	val &= ~(0x3f << shift);

	val |= frac << shift;

	writel_relaxed(val, ref->reg);



	spin_unlock_irqrestore(&mxs_lock, flags);