Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit a8f7703f authored by Dinh Nguyen's avatar Dinh Nguyen Committed by Greg Kroah-Hartman
Browse files

clk: socfpga: stratix10: fix rate caclulationg for cnt_clks 



commit c7ec75ea4d5316518adc87224e3cff47192579e7 upstream.

Checking bypass_reg is incorrect for calculating the cnt_clk rates.
Instead we should be checking that there is a proper hardware register
that holds the clock divider.

Cc: stable@vger.kernel.org
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
Link: https://lkml.kernel.org/r/20190814153014.12962-1-dinguyen@kernel.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent b608a5a2

drivers/clk/socfpga/clk-periph-s10.c

+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ static unsigned long clk_peri_cnt_clk_recalc_rate(struct clk_hw *hwclk, 
	if (socfpgaclk->fixed_div) {

		div = socfpgaclk->fixed_div;

	} else {

		if (!socfpgaclk->bypass_reg)

		if (socfpgaclk->hw.reg)

			div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);

	}